Awesome Open Source
Search
Programming Languages
Languages
All Categories
Categories
About
Search results for verilog vhdl
verilog
x
vhdl
x
137 search results found
Logisim Evolution
⭐
4,251
Digital logic design tool and simulator
Digital
⭐
3,476
A digital logic designer and circuit simulator.
Vexriscv
⭐
2,135
A FPGA friendly 32 bit RISC-V CPU implementation
Cocotb
⭐
1,583
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Spinalhdl
⭐
1,451
Scala based HDL
Neorv32
⭐
1,337
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Clash Compiler
⭐
1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
Fusesoc
⭐
1,065
Package manager and build abstraction tool for FPGA/ASIC development
Awesome Hdl
⭐
830
Hardware Description Languages
Microwatt
⭐
634
A tiny Open POWER ISA softcore written in VHDL 2008
Edalize
⭐
573
An abstraction library for interfacing EDA tools
Openwifi Hw
⭐
560
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Riscv_vhdl
⭐
552
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Hal
⭐
490
HAL – The Hardware Analyzer
Vscode Teroshdl
⭐
457
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Awesome Open Hardware Verification
⭐
353
A List of Free and Open Source Hardware Verification Tools and Frameworks
Rggen
⭐
261
Code generation tool for configuration and status registers
Hdlconvertor
⭐
258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
Ip Cores
⭐
214
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
Degate
⭐
212
A modern and open-source cross-platform software for chips reverse engineering.
Hwt
⭐
189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Degate
⭐
151
Open source software for chip reverse engineering.
Fomu Workshop
⭐
148
Support files for participating in a Fomu workshop
Hdl_checker
⭐
136
Repurposing existing HDL tools to help writing better code
Image Processing
⭐
123
Image Processing Toolbox in Verilog using Basys3 FPGA
Icemu
⭐
113
Emulate Integrated Circuits at the logic level
Tinytpu
⭐
111
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Ivtest
⭐
95
Regression test suite for Icarus Verilog. (OBSOLETE)
Vhd2vl
⭐
91
Bazel_rules_hdl
⭐
90
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
Jt51
⭐
74
YM2151 clone in verilog. FPGA proven.
Symbolator
⭐
73
HDL symbol generator
J1sc
⭐
72
A reimplementation of a tiny stack CPU
Intfftk
⭐
56
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Ipxact2systemverilog
⭐
55
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
Vim Hdl
⭐
53
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
Spam 1
⭐
53
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cp
Hdlparse
⭐
51
Simple parser for extracting VHDL documentation
Hdelk
⭐
50
Web-based HDL diagramming tool
Synthesijer
⭐
47
Getting Started
⭐
46
List of ideas for getting started with TimVideos projects
Neorv32 Setups
⭐
44
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
Xpm_vhdl
⭐
38
A translation of the Xilinx XPM library to VHDL for simulation purposes
Fpu
⭐
37
IEEE 754 floating point library in system-verilog and vhdl
Spinalcrypto
⭐
36
SpinalHDL - Cryptography libraries
Vboard
⭐
34
Virtual development board for HDL design
Docker
⭐
34
Scripts to build and use docker images including GHDL
Hwtlib
⭐
33
hardware library for hwt (= ipcore repo)
Screen Pong
⭐
33
Pong game in a free FPGA.
Chacha
⭐
32
Verilog 2001 implementation of the ChaCha stream cipher.
Fp23fftk
⭐
31
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
Wiki
⭐
31
Xeda
⭐
30
Cross EDA Abstraction and Automation
Ophidian
⭐
29
Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
Verilog Vcd Parser
⭐
28
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
Hdlconvertorast
⭐
25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
Formal_hw_verification
⭐
23
Trying to verify Verilog/VHDL designs with formal methods and tools
Spaceinvadersfpgagame
⭐
23
Verilog implementation of the classic arcade game Space Invaders for the Zedboard FPGA board
Usb De2 Fpga
⭐
22
Hardware interface for USB controller on DE2 FPGA Platform
Edif2qmasm
⭐
21
Run hardware descriptions on a quantum annealer
Paas_v1.0
⭐
20
PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
Design And Asic Implementation Of 32 Point Fft Processor
⭐
20
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a
Fpga Docker
⭐
20
Tools for running FPGA vendor toolchains with Docker
Pythonuberhdl
⭐
20
Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL
Hwthls
⭐
20
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
Fpu Sp
⭐
19
IEEE 754 floating point library in system-verilog and vhdl
Handwritten Digit Recognition Painter
⭐
18
A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.
Picoblaze Library
⭐
18
The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).
Vga Text Generator
⭐
18
A basic VGA text generator for verilog and vhdl
Fpga Ov2640
⭐
17
This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.
Vivado Ci
⭐
17
A simple Vivado (Verilog & VHDL) Continuous Integration tool with seamless integration to Travis-CI
Crcgen
⭐
16
Generator for CRC HDL code (VHDL, Verilog, MyHDL)
Vhd2vl
⭐
16
vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
Netlist Verilog
⭐
16
Netlist and Verilog Haskell Package
Vcnn
⭐
16
Verilog Convolutional Neural Network on PYNQ
Sdram_controller
⭐
16
Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)
Second_order_sigma_delta_dac
⭐
15
A comparison of 1st and 2nd order sigma delta DAC for FPGA
Math
⭐
15
Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
Vproc
⭐
14
Virtual processor co-simulation element for Verilog and VHDL environments
Rggen Sample Testbench
⭐
14
Awesome Hdl
⭐
14
A curated list of awesome HDL, libraries, typical implementation and references.
Digital Resources
⭐
14
Doppler
⭐
14
Doppler effect on WaveForms
Waveview
⭐
14
Digital Waveform Viewer
Ulx3s.github.io
⭐
12
community projects that can be used with the ULX3S FPGA ESP32 board
Omi_device_ice
⭐
12
An example OMI Device FPGA with 2 DDR4 memory ports
Spectrum
⭐
12
Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.
Vextproj
⭐
12
VEXTPROJ - the version control friendly system for creation of Vivado projects
Spinaldev
⭐
12
Docker Development Environment for SpinalHDL
Digital Hardware Modelling
⭐
11
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
Cryptocores
⭐
11
cryptography ip-cores in vhdl / verilog
Orbit
⭐
11
An HDL package manager.
Aws Fpga Firesim
⭐
11
AWS Shell for FireSim
Pacman Tangnano9k
⭐
11
A Pac-Man Arcade implementation for the TangNano9K using HDMI
Pyedaa.projectmodel
⭐
10
An abstract model of EDA tool projects.
Jagnetlists
⭐
10
Atari Jaguar netlists compiler
Verilog Basic
⭐
10
learn the combinational and sequential logic circuit.
Blp
⭐
9
Blinking Led Project
Fliplot
⭐
9
HTML & Js based VCD viewer
Source_to_inst
⭐
9
This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.
Related Searches
Verilog Fpga (1,343)
Fpga Vhdl (845)
Cpu Verilog (330)
Vhdl Xilinx (314)
Verilog Xilinx (265)
Python Verilog (258)
Verilog Rtl (217)
Verilog Systemverilog (211)
C Plus Plus Verilog (165)
C Verilog (155)
1-100 of 137 search results
Next >
Privacy
|
About
|
Terms
|
Follow Us On Twitter
Copyright 2018-2024 Awesome Open Source. All rights reserved.