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Search results for c verilog
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verilog
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76 search results found
Openwifi
⭐
3,363
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Nyuziprocessor
⭐
1,863
GPGPU microprocessor architecture
8bitworkshop
⭐
465
web-based IDE for 8-bit programming and Verilog development
Ao486
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185
The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.
Qflow
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164
Qflow full end-to-end digital synthesis flow for ASIC designs
Metron
⭐
143
A C++ to Verilog translation tool with some basic guarantees that your code will work.
Openfpgaduino
⭐
135
All open source file and project for OpenFPGAduino project
Zynq7010_eink_controller
⭐
133
这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS
Icemu
⭐
113
Emulate Integrated Circuits at the logic level
Z3
⭐
111
A Verilog implementation of the Infocom Z-Machine V3. With BIOS and benchmarks. Verified in hardware.
Srv32
⭐
109
Simple 3-stage pipeline RISC-V processor
Icestation 32
⭐
107
Compact FPGA game console
Mcpu
⭐
104
MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD
Dparser
⭐
94
A Scannerless GLR parser/parser generater.
Fpga Rocket Chip
⭐
79
Wrapper for Rocket-Chip on FPGAs
Keyboard
⭐
72
客制化机械键盘——从0开始全套资料
Tree Sitter Verilog
⭐
70
SystemVerilog grammar for tree-sitter
Verilog Parser
⭐
68
A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
Sol 1
⭐
57
Sol-1: A CPU/Computer System made from 74 series logic.
Cep
⭐
53
The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
Pcievhost
⭐
49
PCIe (1.0a to 2.0) Virtual host model for verilog
Spu32
⭐
48
Small Processing Unit 32: A compact RV32I CPU written in Verilog
Pdp6
⭐
45
PDP-6 Emulator
Super Miyamoto Sprint
⭐
41
Homebrew game for homebrew FPGA game console
Usb_sniffer
⭐
40
High Speed USB 2.0 capture device based on miniSpartan6+
Fpga101 Workshop
⭐
38
FPGA 101 - Workshop materials
Grassrootsstartup Computervsion Zynq
⭐
35
Open Src Cvc
⭐
32
Mirror of tachyon-da cvc Verilog simulator
Riscv_cpu
⭐
30
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
Shunt
⭐
29
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
Pslse
⭐
28
Power Service Layer Simulation Engine
Gen_amba
⭐
28
AMBA bus generator including AXI, AHB, and APB
Cse Mit Manipal
⭐
26
The collective code required for completing a 4-year B.Tech Computer Science Engineering Course.
Yari
⭐
24
YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.
Hust Lab
⭐
22
Labs for Computer Science - c, asm, data structure, csapp, hsi, matlab, digital logic, verilog, compilers, operating systems
Bgbtech_btsr1arch
⭐
17
BtSR1 and BJX2 ISA / CPU Architecture
Grom8
⭐
16
GROM-8 CPU
Sea
⭐
15
Jtag_interface
⭐
14
A template for establishing a JTAG connection between the MCU and FPGA chip on the Arduino MKR Vidor 4000
Vproc
⭐
14
Virtual processor co-simulation element for Verilog and VHDL environments
Vcddiff
⭐
13
Basic VCD comparison tool, for Verilator testing
Fstdumper
⭐
12
Verilog VPI module to dump FST (Fast Signal Trace) databases
Maple
⭐
12
MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).
Synverll
⭐
12
Sknobs
⭐
11
A utility for processing command line arguments
Zynq Aes
⭐
11
AES hardware engine for Xilinx Zynq platform
Toast Rv32i
⭐
11
A Pipelined RISC-V RV32I Core in Verilog
Atari_xlxe_sd_cartridge
⭐
11
Atari XL/XE SD cartridge
Icore
⭐
10
in-line FPGA-CPU协同分组处理
Nldb
⭐
10
Verilog netlist parser/database (derived from http://nldb.sourceforge.net)
Verilog Snippets
⭐
10
Verilog Snippets for partial fulfilment of CS-F342 Computer Architecture,BITS Pilani
Ariths Gen
⭐
9
Generator of arithmetic circuits (multipliers, adders) and approximate circuits
Herring 6502
⭐
9
Modular 8-bit computer designed around the 65C02 CPU and supporting I/O chips
Teardown2019 Workshop
⭐
8
Workshop Example code for Fomu at Teardown 2019
Riscv32_lcc
⭐
8
Sock.sv
⭐
8
A simple TCP socket library for system verilog. Using the system verilog DPI, allows the user to read / write lines from a TCP socket connection.
Sgbm_fpga
⭐
8
This repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog. Code in this repo contains both C++ SGBM simulation code and PS-PL vitis-vivado project. Tutorial and the video attached thoroughly explain my designation in detail, although made in Chinese hhhhh.
Silver
⭐
8
SILVER - Statistical Independence and Leakage Verification
Gtuedu
⭐
7
Gebze Technical University
Clash Cosim
⭐
7
Co-simulation between CλaSH and standardized HDLs (only Verilog currently)
Macsehw
⭐
7
Macintosh SE Hardware Designs
Cic_prune
⭐
6
A C version of Rick Lyon's Matlab implementation of Hogenauer's CIC filter register pruning algorithm
Ulx3s Bluetooth Gamepad
⭐
6
Bluetooth gamepad receiver demo using ULX3S FPGA board + ESP32
Verilog Parser
⭐
6
A verilog parser
Libxbf
⭐
6
Xilinx Bitstream Format Library. Easily read .bit files from C programs.
Cse Lab Solutions
⭐
6
Comprehensive CSE Lab Solutions repo; encompassing all my lab manuals, codes, documents, and endsem questions from my B.Tech program (2020-2024).
Vbpp
⭐
6
Verilog PreProcessor.
Libcircuit
⭐
6
libCircuit is a C++ Library for EDA software development
Dewey
⭐
6
C version of PERSHING, a place-and-route tool for Minecraft Redstone circuits
Forzando Brutalmente Md5
⭐
5
Phloppy_0
⭐
5
Commodore Amiga floppy drive emulator
Computer Engineering Projects
⭐
5
Digital computer structure, Hardware Design Lab & Introduction to Computers for computer engineering projects in C, C#, Assembly, Pspice.
Gnucap
⭐
5
Gnucap is a analog and mixed signal circuit simulator. Go to gnucap.org for latest information. This is an unofficial clone of the repo. This holds the work done for GSoC 2012 with GNU Project. Go to official repo:
Muraxarduino
⭐
5
A version of f32c/arduino that works with the SpinalHDL Vexriscv Murax SoC
Fpga_test_soc
⭐
5
A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
Verilog Sim Benchmarks
⭐
5
Verilog Simulator Benchmarks, a fork from verilator website
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1-76 of 76 search results
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