Pcievhost

PCIe (1.0a to 2.0) Virtual host model for verilog
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Project NameStarsDownloadsRepos Using ThisPackages Using ThisMost Recent CommitTotal ReleasesLatest ReleaseOpen IssuesLicenseLanguage
Fpga_based_cnn113
7 years ago3Verilog
FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
Pcievhost49
2 months agogpl-3.0C
PCIe (1.0a to 2.0) Virtual host model for verilog
Uhd Fairwaves22
4 months ago10Verilog
Fairwaves version of the UHD drivers, tweaked to support Fairwaves UmTRX.
Sdram_controller16
8 years ago2Python
Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)
Nysa14
7 years ago3otherPython
FPGA Development toolset
Ssith Aws Fpga12
3 years agobsd-2-clauseVerilog
Host software for running SSITH processors on AWS F1 FPGAs
Sata3_host_controller9
6 years agoVerilog
It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
Qemu Hdl Cosim9
3 years agomitVerilog
VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
Pciebench Netfpga8
6 years agootherVerilog
pcie-bench code for NetFPGA/VCU709 cards
Bwa Mem Sw8
9 years agoVerilog
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