Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Fpga_based_cnn | 113 | 7 years ago | 3 | Verilog | ||||||
FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform. | ||||||||||
Pcievhost | 49 | 2 months ago | gpl-3.0 | C | ||||||
PCIe (1.0a to 2.0) Virtual host model for verilog | ||||||||||
Uhd Fairwaves | 22 | 4 months ago | 10 | Verilog | ||||||
Fairwaves version of the UHD drivers, tweaked to support Fairwaves UmTRX. | ||||||||||
Sdram_controller | 16 | 8 years ago | 2 | Python | ||||||
Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/) | ||||||||||
Nysa | 14 | 7 years ago | 3 | other | Python | |||||
FPGA Development toolset | ||||||||||
Ssith Aws Fpga | 12 | 3 years ago | bsd-2-clause | Verilog | ||||||
Host software for running SSITH processors on AWS F1 FPGAs | ||||||||||
Sata3_host_controller | 9 | 6 years ago | Verilog | |||||||
It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface. | ||||||||||
Qemu Hdl Cosim | 9 | 3 years ago | mit | Verilog | ||||||
VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs | ||||||||||
Pciebench Netfpga | 8 | 6 years ago | other | Verilog | ||||||
pcie-bench code for NetFPGA/VCU709 cards | ||||||||||
Bwa Mem Sw | 8 | 9 years ago | Verilog | |||||||