Qflow
Qflow full end-to-end digital synthesis flow for ASIC designs
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Poc | 324 | 4 years ago | 31 | other | VHDL | |||||
| IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany | ||||||||||
| Livehd | 192 | 3 months ago | 4 | June 06, 2018 | 11 | other | Verilog | |||
| Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation | ||||||||||
| Async_fifo | 173 | a year ago | other | Verilog | ||||||
| A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog | ||||||||||
| Qflow | 164 | 3 months ago | 38 | C | ||||||
| Qflow full end-to-end digital synthesis flow for ASIC designs | ||||||||||
| Logic | 121 | 4 years ago | apache-2.0 | SystemVerilog | ||||||
| CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs. | ||||||||||
| My Verilog Examples | 22 | 10 months ago | mit | Verilog | ||||||
| A place to keep my synthesizable verilog examples. | ||||||||||
| Design And Asic Implementation Of 32 Point Fft Processor | 20 | 5 months ago | mit | Verilog | ||||||
| I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage. | ||||||||||
| Comet | 10 | 4 years ago | C | |||||||
| RISC-V ISA based 32-bit processor written in HLS | ||||||||||
| S Link | 8 | 3 years ago | 3 | mit | Verilog | |||||
| An Open Source Link Protocol and Controller | ||||||||||
| Riscv Asic | 8 | 6 years ago | ||||||||
| RISC-V ASIC design reference | ||||||||||
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