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Search results for verilog

2,186 search results found

Logisim Evolution ⭐ 4,251

Digital logic design tool and simulator

Chisel ⭐ 3,685

Chisel: A Modern Hardware Design Language

Digital ⭐ 3,476

A digital logic designer and circuit simulator.

Openwifi ⭐ 3,363

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Iverilog ⭐ 2,521

Vexriscv ⭐ 2,135

A FPGA friendly 32 bit RISC-V CPU implementation

Verilator ⭐ 1,934

Verilator open-source SystemVerilog simulator and lint system

Nyuziprocessor ⭐ 1,863

GPGPU microprocessor architecture

Darkriscv ⭐ 1,795

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog Ethernet ⭐ 1,768

Verilog Ethernet components for FPGA implementation

E200_opensource ⭐ 1,688

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Icestudio ⭐ 1,621

❄️ Visual editor for open FPGA boards

Fromthetransistor ⭐ 1,607

From the Transistor to the Web Browser, a rough outline for a 12 week course

Cocotb ⭐ 1,583

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Wujian100_open ⭐ 1,456

IC design and development should be faster，simpler and more reliable

Spinalhdl ⭐ 1,451

Scala based HDL

Circt ⭐ 1,431

Circuit IR Compilers and Tools

Corundum ⭐ 1,354

Open source FPGA-based NIC and platform for in-network compute

Neorv32 ⭐ 1,337

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Clash Compiler ⭐ 1,336

Haskell to VHDL/Verilog/SystemVerilog compiler

Basic_verilog ⭐ 1,333

Must-have verilog systemverilog modules

HDL libraries and projects

RTL, Cmodel, and testbench for NVDLA

Silice ⭐ 1,199

Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.

SERV - The SErial RISC-V CPU

Openlane ⭐ 1,148

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Zipcpu ⭐ 1,139

A small, light weight, RISC CPU soft core

Verilog Axi ⭐ 1,113

Verilog AXI components for FPGA implementation

Platformio Vscode Ide ⭐ 1,104

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Openroad ⭐ 1,102

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Metroboy ⭐ 1,089

A repository of gate-level simulators and tools for the original Game Boy.

XLS: Accelerated HW Synthesis

Fusesoc ⭐ 1,065

Package manager and build abstraction tool for FPGA/ASIC development

Amiga2000 Gfxcard ⭐ 960

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

Openc910 ⭐ 949

OpenXuantie - OpenC910 Core

Vtr Verilog To Routing ⭐ 925

Verilog to Routing -- Open Source CAD Flow for FPGA Research

The USRP™ Hardware Driver Repository

Chisel Bootcamp ⭐ 863

Generator Bootcamp Material: Learn Chisel the Right Way

Bluespec Compiler (BSC)

Verilog Pcie ⭐ 844

Verilog PCI express components

Awesome Hdl ⭐ 830

Hardware Description Languages

E203_hbirdv2 ⭐ 741

The Ultra-Low Power RISC-V Core

Openfpga ⭐ 692

An Open-source FPGA IP Generator

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

🌱 Open source ecosystem for open FPGA boards

Verilog2factorio ⭐ 659

This project will compile verilog (a hardware description language) into factorio blueprints.

Microwatt ⭐ 634

A tiny Open POWER ISA softcore written in VHDL 2008

Riscv Sodor ⭐ 619

educational microarchitectures for risc-v isa

Genetic circuit design automation

Usb_c_industrial_camera_fpga_usb3 ⭐ 610

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

Minecrafthdl ⭐ 595

A Verilog synthesis flow for Minecraft redstone circuits

Verilog Practice ⭐ 593

HDLBits website practices & solutions

An open source GPU based off of the AMD Southern Islands ISA.

Edalize ⭐ 573

An abstraction library for interfacing EDA tools

Hardcaml ⭐ 571

Hardcaml is an OCaml library for designing hardware.

Openwifi Hw ⭐ 560

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Riscv_vhdl ⭐ 552

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Openpiton ⭐ 545

The OpenPiton Platform

SystemVerilog compiler and language services

HAL – The Hardware Analyzer

Projf Explore ⭐ 478

Project F brings FPGAs to life with exciting open-source designs you can build on.

Platformio Atom Ide ⭐ 474

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

8bitworkshop ⭐ 465

web-based IDE for 8-bit programming and Verilog development

Vscode Teroshdl ⭐ 457

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Beagle_sdr_gps ⭐ 446

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

Cfu Playground ⭐ 434

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.

mor1kx - an OpenRISC 1000 processor IP core

Cascade ⭐ 432

A Just-In-Time Compiler for Verilog from VMware Research

SystemVerilog to Verilog conversion

Ucr Eecs168 Lab ⭐ 423

The lab schedules for EECS168 at UC Riverside

Wb2axip ⭐ 409

Bus bridges and other odds and ends

VRoom! RISC-V CPU

Graphics Gremlin ⭐ 399

Open source retro ISA video card

Kianriscv ⭐ 396

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .

Apicula ⭐ 390

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Verilogboy ⭐ 388

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

Bsv_tutorial_cn ⭐ 381

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开

Risc V Single Cycle Cpu ⭐ 380

A RISC-V 32bit single-cycle CPU written in Logisim

SystemVerilog language server

Opentimer ⭐ 368

A High-performance Timing Analysis Tool for VLSI Systems

RISC-V CPU Core (RV32IM)

Verilog I2c ⭐ 362

Verilog I2C interface for FPGA implementation

Mips Cpu ⭐ 356

MIPS CPU implemented in Verilog

Awesome Open Hardware Verification ⭐ 353

A List of Free and Open Source Hardware Verification Tools and Frameworks

Sv Parser ⭐ 348

SystemVerilog parser library fully compliant with IEEE 1800-2017

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Surelog ⭐ 325

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Verigpu ⭐ 323

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Icesugar ⭐ 320

iCESugar FPGA Board (base on iCE40UP5k)

Fpga Foc ⭐ 319

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Verilog_systemverilog.vim ⭐ 317

Verilog/SystemVerilog Syntax and Omni-completion

Tillitis Key1 ⭐ 312

Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑

Various HDL (Verilog) IP Cores

Biriscv ⭐ 300

32-bit Superscalar RISC-V CPU

Reduceron ⭐ 296

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

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