Awesome Open Source
Search
Programming Languages
Languages
All Categories
Categories
About
Search results for cpu verilog
cpu
x
verilog
x
145 search results found
Vexriscv
⭐
2,135
A FPGA friendly 32 bit RISC-V CPU implementation
Darkriscv
⭐
1,795
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
E200_opensource
⭐
1,688
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Neorv32
⭐
1,337
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Zipcpu
⭐
1,139
A small, light weight, RISC CPU soft core
E203_hbirdv2
⭐
741
The Ultra-Low Power RISC-V Core
Riscv_vhdl
⭐
552
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Kianriscv
⭐
396
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .
Risc V Single Cycle Cpu
⭐
380
A RISC-V 32bit single-cycle CPU written in Logisim
Riscv
⭐
364
RISC-V CPU Core (RV32IM)
Mips Cpu
⭐
356
MIPS CPU implemented in Verilog
Biriscv
⭐
300
32-bit Superscalar RISC-V CPU
Scamp Cpu
⭐
279
A homebrew 16-bit CPU with a homebrew Unix-like-ish operating system.
Ustc Rvsoc
⭐
261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。
Warp V
⭐
220
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
Fpga Chip8
⭐
167
CHIP-8 console on FPGA
Tekno Kizil
⭐
129
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
Toooba
⭐
126
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
Icestation 32
⭐
107
Compact FPGA game console
Schoolmips
⭐
106
CPU microarchitecture, step by step
Mcpu
⭐
104
MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD
Dinocpu
⭐
101
A teaching-focused RISC-V CPU design used at UC Davis
Oldland Cpu
⭐
89
Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
Mdec
⭐
88
Attempt to verilog Implementation of Playstation 1 (PSX) chips.
Lispmicrocontroller
⭐
85
A microcontroller that natively executes a simple LISP dialect
Xcrypto
⭐
80
XCrypto: a cryptographic ISE for RISC-V
Mips32 Cpu
⭐
73
奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)
Cpu
⭐
73
A very primitive but hopefully self-educational CPU in Verilog
J1sc
⭐
72
A reimplementation of a tiny stack CPU
Naivemips Hdl
⭐
63
Naïve MIPS32 SoC implementation
Pasc
⭐
62
Parallel Array of Simple Cores. Multicore processor.
Nscscc Wiki
⭐
60
NSCSCC 信息整合
Cscvon8
⭐
58
A crazy small 8-bit CPU built with only seventeen 7400-series chips.
Sol 1
⭐
57
Sol-1: A CPU/Computer System made from 74 series logic.
Reindeer
⭐
56
PulseRain Reindeer - RISCV RV32I[M] Soft CPU
Riscy Soc
⭐
54
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
8 Bits Risc Cpu Verilog
⭐
53
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。
Spam 1
⭐
53
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cp
Spu32
⭐
48
Small Processing Unit 32: A compact RV32I CPU written in Verilog
Ultramips_nscscc
⭐
47
UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
Vexriscvsoftcorecontest2018
⭐
46
Soc
⭐
45
An experimental System-on-Chip with a custom compiler toolchain.
Mc6809
⭐
45
Cycle-Accurate MC6809/E implementation, Verilog
Hrm Cpu
⭐
43
Human Resource Machine - CPU Design #HRM
Rj32
⭐
42
A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.
Basic Simd Processor Verilog Tutorial
⭐
41
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
Fuxi
⭐
40
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
Bit_nscscc_suggestion
⭐
38
为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助
Quafu
⭐
35
A small SoC with a pipeline 32-bit RISC-V CPU.
R8051
⭐
34
8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
Phoenix
⭐
34
phoeniX RISC-V Processor
Risc V Cpu
⭐
34
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
Riscv_cpu
⭐
30
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
Risc V
⭐
29
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
Observer
⭐
28
Proteus
⭐
27
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
Riscv_piccolo_v1
⭐
26
Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
Computer Architecture Task 2
⭐
25
Riscv32 CPU Project
Mips Cpu
⭐
25
💻 A 5-stage pipeline MIPS CPU implementation in Verilog.
S6soc
⭐
24
CMod-S6 SoC
Diy_openmips
⭐
24
實作《自己動手寫CPU》書上的程式碼
Arm9 Compatible Soft Cpu Core
⭐
23
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
Fpga_threelevelstorage
⭐
23
【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。
Kisc V
⭐
21
KISCV, a KISS principle riscv32i CPU
Tinycpu
⭐
21
Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.
Paas_v1.0
⭐
20
PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
Buaa_co
⭐
18
2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
Scarv Cpu
⭐
18
SCARV: a side-channel hardened RISC-V platform
Chad
⭐
18
A self-hosting Forth for J1-style CPUs
Grom8
⭐
16
GROM-8 CPU
Tinyfpga Bx Game Soc
⭐
16
A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games
Digital Resources
⭐
14
Icozip
⭐
14
A ZipCPU demonstration port for the icoboard
Dmgcpu
⭐
14
DMG CPU Core Reverse Engineering
Gameduino
⭐
14
My own version of the @JamesBowman's Gameduino file repository
Riscv Atom
⭐
14
An open-source 32-bit RISC-V soft-core processor for FPGAs.
Coexperiment_repo
⭐
13
计算机组成原理实验 NUAA Spring 2017
Risc8
⭐
13
Mostly AVR compatible FPGA soft-core
Mesabusprotocol
⭐
13
Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
Srgh Matrix Trinity
⭐
12
XBOX 360 advanced glitching - Reverse Engineered using a logic analyzer.
Spinaldev
⭐
12
Docker Development Environment for SpinalHDL
Cpu
⭐
12
CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.
Ada Picorv32 Example
⭐
12
Example of Ada code running on the PicoRV32 RISC-V CPU for FPGA
Veriscala
⭐
12
Riscv Cpu
⭐
11
SJTU Computer Architecture(1) Hw
Fpganes_release
⭐
11
Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog
Elec50010 2020 Verilog Lab
⭐
11
Verilog lab material for ELEC50010 class
Simple_mips_cpu
⭐
11
A simple MIPS CPU, for fun.
Mips Cpu
⭐
11
The Verilog implementation of five-stage-pipelined MIPS CPU (Classic RISC pipeline)
Pythondata Cpu Rocket
⭐
10
Python module containing verilog files for rocket cpu (for use with LiteX).
Icore
⭐
10
in-line FPGA-CPU协同分组处理
Croyde Riscv
⭐
10
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
Mera400f
⭐
10
MERA-400 in an FPGA
Brainf__k_cpu
⭐
10
A CPU that executes brainf**k language. Can be synthesized on FPGA
Nano Cpu32k
⭐
10
Superscalar out-of-order RISC core (with Cache& MMU) and SoC, supporting GNU toolchain & Linux 4.20 kernel, having been verified on Xilinx Kintex-7 FPGA.
Mips Architecture Cpu Design
⭐
9
BUAA SCSE - Computer Organization - Pipeline CPU design
Mips Simulator
⭐
9
💻 A 5-stage pipeline MIPS CPU design in Haskell.
Computer System
⭐
9
同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植
Udarkrisc
⭐
9
u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
Bk0010
⭐
9
БК - в ФПГА!
Related Searches
C Cpu (1,683)
Verilog Fpga (1,343)
C Plus Plus Cpu (1,247)
Python Cpu (1,222)
Gpu Cpu (1,114)
Cpu Arm (442)
Python Verilog (267)
Verilog Xilinx (265)
Verilog Vhdl (249)
Assembly Cpu (241)
1-100 of 145 search results
Next >
Privacy
|
About
|
Terms
|
Follow Us On Twitter
Copyright 2018-2024 Awesome Open Source. All rights reserved.