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Search results for python verilog
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verilog
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159 search results found
Cocotb
⭐
1,583
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Fusesoc
⭐
1,065
Package manager and build abstraction tool for FPGA/ASIC development
Apio
⭐
671
🌱 Open source ecosystem for open FPGA boards
Edalize
⭐
573
An abstraction library for interfacing EDA tools
Openpiton
⭐
545
The OpenPiton Platform
Hal
⭐
490
HAL – The Hardware Analyzer
Awesome Open Hardware Verification
⭐
353
A List of Free and Open Source Hardware Verification Tools and Frameworks
Pymtl3
⭐
344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
Nngen
⭐
281
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
Veriloggen
⭐
275
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
Hdlconvertor
⭐
258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
F4pga Arch Defs
⭐
245
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Magma
⭐
234
magma circuits
Verilog Generator Of Neural Net Digit Detector For Fpga
⭐
231
Verilog Generator of Neural Net Digit Detector for FPGA
Chips 2.0
⭐
205
FPGA Design Suite based on C to Verilog design flow.
Hwt
⭐
189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Pymtl
⭐
149
Python-based hardware modeling framework
Hdl_checker
⭐
136
Repurposing existing HDL tools to help writing better code
Image Processing
⭐
123
Image Processing Toolbox in Verilog using Basys3 FPGA
Cocotb Test
⭐
114
Unit testing for cocotb
Haasoscope
⭐
107
Docs, design, firmware, and software for the Haasoscope
Openlane2
⭐
99
The next generation of OpenLane, rewritten from scratch with a modular architecture
Verilog Lfsr
⭐
92
Fully parametrizable combinatorial parallel LFSR/CRC module
Opencgra
⭐
90
OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
Vlsiffra
⭐
89
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
Lispmicrocontroller
⭐
85
A microcontroller that natively executes a simple LISP dialect
Skynet
⭐
75
Circuitgraph
⭐
74
Tools for working with circuits as graphs in python
Symbolator
⭐
73
HDL symbol generator
Spydrnet
⭐
66
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
Hdlgen
⭐
60
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
Verilog Wishbone
⭐
59
Verilog wishbone components
Svut
⭐
59
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Kratos
⭐
57
⚔️ Debuggable hardware generator
Sump2
⭐
57
open-source logic analyzer for FPGAs
Ipxact2systemverilog
⭐
55
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
Vim Hdl
⭐
53
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
Corsair
⭐
52
Control and Status Register map generator for HDL projects
Hdlparse
⭐
51
Simple parser for extracting VHDL documentation
Autosva
⭐
50
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
Fasoc
⭐
50
Peakrdl
⭐
48
Control and status register code generator toolchain
Litex Cnc
⭐
44
Generic CNC firmware and driver for FPGA cards which are supported by LiteX
Sphinxcontrib Hdl Diagrams
⭐
43
Sphinx Extension which generates various types of diagrams from Verilog code.
Vlsistuff
⭐
42
ideas and eda software for vlsi design
Tt05 Psg Sn76489
⭐
42
TinyTapeout submission with the SN76489 Digital Complex Sound Generator (DCSG) programmable sound generator (PSG) chip from Texas Instruments.
Pycoram
⭐
42
Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
Fault
⭐
40
A Python package for testing hardware (part of the magma ecosystem)
Basil
⭐
38
A data acquisition framework in Python and Verilog.
Pychip Py Hcl
⭐
35
A Hardware Construct Language
Cosa
⭐
35
CoreIR Symbolic Analyzer
Pydigitalwavetools
⭐
34
Python library for operations with VCD and other digital wave files
Verilog Gadget
⭐
34
🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.
Hwtlib
⭐
33
hardware library for hwt (= ipcore repo)
Pyverilator
⭐
32
Python wrapper for verilator model
Simplez Fpga
⭐
32
Verilog implementation of the educational "Simplez" processor
Platform Lattice_ice40
⭐
31
Lattice iCE40: development platform for PlatformIO
Pyverilog
⭐
30
Python-based Verilog Parser (currently Netlist only)
Xeda
⭐
30
Cross EDA Abstraction and Automation
Shunt
⭐
29
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
Pymtl3 Net
⭐
28
Project repo for the POSH on-chip network generator
Deepsocflow
⭐
28
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
Manthan
⭐
26
Manthan for Boolean function synthesis
Crash_course_for_new_members
⭐
26
Deep Learning & VLSI Crash Course for New Members
Hdlconvertorast
⭐
25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
Lizard
⭐
25
Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
Pergola_projects
⭐
24
My pergola FPGA projects
Bsg_sv2v
⭐
23
A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
Vim Verilog Instance
⭐
22
verilog_instance.vim: create instantiation of ports from port declaration
F4pga Sdf Timing
⭐
21
Python library for working Standard Delay Format (SDF) Timing Annotation files.
Pythonuberhdl
⭐
20
Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL
Hwthls
⭐
20
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
Mixedsim
⭐
19
Hardware Design Tool - Mixed Signal Simulation with Verilog
Nicotb
⭐
19
A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COroutine TestBench.
Pyverilog_toolbox
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17
Verilog Automatic
⭐
17
Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3
Vivado Ci
⭐
17
A simple Vivado (Verilog & VHDL) Continuous Integration tool with seamless integration to Travis-CI
Crcgen
⭐
16
Generator for CRC HDL code (VHDL, Verilog, MyHDL)
Sdram_controller
⭐
16
Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)
Chipy
⭐
15
chipy hdl
Hfbs
⭐
15
a hardware-friendly bilateral solver
Ipgen
⭐
15
IP-core package generator for AXI4/Avalon
Scratchip
⭐
15
scratchip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier.
Flicker Noise
⭐
15
How to correctly write a flicker-noise model for RF simulation.
Mobile Fpga Bluetooth Midi
⭐
14
Interactive BLE MIDI demo using an iOS app (SwiftUI), an ESP32 (Python) and an FPGA (Verilog)
Anasymod
⭐
14
A framework for FPGA emulation of mixed-signal systems
Lake
⭐
14
Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.
Nysa
⭐
14
FPGA Development toolset
Sublimelinter Contrib Verilator
⭐
13
👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)
Fpga Sdrlib
⭐
13
Verilog modules for software-defined radio.
Study Materials
⭐
12
Lit3rick
⭐
12
An up5k board to manage pulse-echo ultrasound acquisition.
Cpu
⭐
12
CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.
Pershing
⭐
11
An automatic place-and-route tool for Minecraft redstone circuits
Rules_vivado
⭐
11
Bazel rules for Xilinx Vivado
Fpganes_release
⭐
11
Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog
Verilog Mersenne
⭐
11
Verilog implementation of Mersenne Twister PRNG
Nirah
⭐
11
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
Vcdvis
⭐
11
VCD visualizer: view your waveforms in ASCII format, or export them to TikZ figures.
Nmigen Examples
⭐
10
I want to learn [n]Migen.
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