Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Opentimer | 368 | a year ago | 48 | other | Verilog | |||||
A High-performance Timing Analysis Tool for VLSI Systems | ||||||||||
Circuitgraph | 74 | 1 | a year ago | 7 | September 24, 2021 | 11 | mit | Verilog | ||
Tools for working with circuits as graphs in python | ||||||||||
Hdelk | 50 | 2 years ago | 7 | apache-2.0 | JavaScript | |||||
Web-based HDL diagramming tool | ||||||||||
Yahdl | 15 | 6 years ago | 2 | bsd-3-clause | Java | |||||
A programming language for FPGAs. | ||||||||||
Netlist Graph | 8 | 7 years ago | mit | Java | ||||||
Java library for parsing and manipulating graph representations of gate-level Verilog netlists | ||||||||||
Sparkfun Rgb Bar Graph | 6 | 10 months ago | Verilog | |||||||