Cosa
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Koika | 84 | 2 years ago | 7 | gpl-3.0 | Coq | |||||
| A core language for rule-based hardware design 🦑 | ||||||||||
| Cosa | 35 | | 1 | 1 | 3 years ago | 16 | June 03, 2019 | 5 | other | Python |
| CoreIR Symbolic Analyzer | ||||||||||
| Formal_hw_verification | 23 | 3 years ago | lgpl-3.0 | VHDL | ||||||
| Trying to verify Verilog/VHDL designs with formal methods and tools | ||||||||||
| Hardware | 18 | a year ago | bsd-3-clause | Standard ML | ||||||
| Verilog development and verification project for HOL4 | ||||||||||
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