Bsg_sv2v
A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Riscv Bitmanip | 174 | a year ago | 44 | cc-by-4.0 | Makefile | |||||
| Working draft of the proposed RISC-V Bitmanipulation extension | ||||||||||
| Openfpgaduino | 135 | 6 years ago | 6 | agpl-3.0 | Makefile | |||||
| All open source file and project for OpenFPGAduino project | ||||||||||
| Bsg_sv2v | 23 | a year ago | 2 | bsd-3-clause | Python | |||||
| A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible. | ||||||||||
| Fpga Docker | 20 | 3 years ago | 1 | Makefile | ||||||
| Tools for running FPGA vendor toolchains with Docker | ||||||||||
| Ice40_8bitworkshop | 8 | 4 years ago | other | Verilog | ||||||
| "Designing Video Game Hardware in Verilog" in iCE40HX8K Breakout Board. | ||||||||||
| Upduino Example | 6 | a year ago | other | Makefile | ||||||
| Example UPduino project setup for Linux, macOS and WIndows+WSL for synthesis and simulation | ||||||||||
| Vbpp | 6 | 9 years ago | other | C | ||||||
| Verilog PreProcessor. | ||||||||||
| Pyjer | 5 | 8 years ago | 4 | mit | Makefile | |||||
| A Framework for Prototyping of IoT Devices with High Level Synthesis Tools and SoC | ||||||||||
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Python
Makefile
Verilog