Awesome Open Source
Awesome Open Source
Combined Topics
verilog x

The Top 6,925 Verilog Open Source Projects on Github

Categories > Hardware > Verilog
1-100 of 6,925 projects

Related Projects

Verilog Fpga Projects (617)
Verilog Systemverilog Projects (173)
Verilog Vhdl Projects (144)
Verilog Cpu Projects (114)
Verilog Hdl Projects (114)
Python Verilog Projects (105)
Verilog Risc V Projects (102)
Verilog Rtl Projects (86)
C Verilog Projects (81)
Verilog Xilinx Projects (78)
Verilog Vhdl Fpga Projects (73)
Verilog Fpga Systemverilog Projects (70)
Verilog Vivado Projects (70)
Verilog Hardware Projects (68)
C Plus Plus Verilog Projects (60)
Verilog Fpga Hdl Projects (54)
Verilog Fpga Xilinx Projects (50)
Verilog Fpga Risc V Projects (47)
Verilog Fpga Rtl Projects (47)
Verilog Processor Projects (46)
Verilog Verilator Projects (45)
Verilog Hardware Fpga Projects (44)
Verilog Asic Projects (43)
Verilog Altera Projects (43)
C Verilog Fpga Projects (41)
Python Verilog Fpga Projects (41)
Verilog Simulation Projects (41)
Verilog Fpga Cpu Projects (38)
Verilog Fpga Vivado Projects (38)
Verilog Systemverilog Rtl Projects (37)
Verilog Uart Projects (36)
Verilog Ice40 Projects (36)
Verilog Fpga Asic Projects (34)
Python Verilog Systemverilog Projects (34)
Verilog Fpga Altera Projects (33)
Verilog Eda Projects (32)
Verilog Systemverilog Hdl Projects (30)
Verilog Cpu Risc V Projects (29)
Python Verilog Vhdl Projects (29)
Verilog Fpga Ice40 Projects (28)
Verilog Vhdl Systemverilog Projects (27)
Verilog Fpga Verilator Projects (26)
C Plus Plus Verilog Fpga Projects (26)
Verilog Vhdl Hdl Projects (26)
Verilog Yosys Projects (26)
Verilog Soc Projects (25)
Verilog Synthesis Projects (25)
Verilog Xilinx Vivado Projects (25)
Assembly Verilog Projects (23)
Verilog Icestorm Projects (23)
Verilog Fpga Uart Projects (23)
Python Verilog Hdl Projects (23)
Verilog Lattice Projects (22)
Verilog Vlsi Projects (22)
Verilog Usb Projects (22)
Verilog Fpga Lattice Projects (21)
Verilog Zynq Projects (20)
Verilog Fpga Icestorm Projects (20)
Verilog Systemverilog Asic Projects (20)
Javascript Verilog Projects (19)
Verilog Verification Projects (19)
Verilog Fpga Usb Projects (19)
Verilog Compiler Projects (18)
Verilog Tcl Projects (18)
Verilog Spi Projects (18)
Verilog Fpga Zynq Projects (17)
Verilog Fpga Xilinx Vivado Projects (17)
Verilog Fpga Processor Projects (17)
Verilog Fpga Systemverilog Asic Projects (16)
Verilog Uvm Projects (16)
Verilog Wishbone Projects (16)
Verilog Risc V Rv32i Projects (16)
Verilog Rv32i Projects (16)
Verilog Wishbone Bus Projects (15)
Scala Verilog Projects (15)
Java Verilog Projects (15)
Verilog Simulator Projects (15)
Verilog Fpga Soc Projects (15)
Linux Verilog Projects (14)
Verilog Artix 7 Projects (14)
Verilog Fpga Eda Projects (13)
Verilog Rtl Asic Projects (13)
Verilog Rtl Hdl Projects (13)
Verilog Chisel3 Projects (12)
Verilog Fpga Cpu Risc V Projects (12)
Haskell Verilog Projects (12)
Verilog Systemverilog Verilator Projects (12)
Hacktoberfest Verilog Projects (12)
Verilog Xilinx Altera Projects (12)
Open Source Verilog Projects (12)
Rust Verilog Projects (12)
Verilog Parser Projects (12)
Verilog Systemverilog Uvm Projects (12)
Verilog Chisel Projects (11)
Verilog Hardware Description Language Projects (11)
Python Verilog Vhdl Fpga Projects (11)
Verilog Microcontroller Projects (11)