The Top 6,925 Verilog Open Source Projects on Github

Awesome Open Source

Awesome Open Source

Combined Topics

Advertising 📦 9

Application Programming Interfaces 📦 120

Applications 📦 181

Artificial Intelligence 📦 72

Blockchain 📦 70

Build Tools 📦 111

Cloud Computing 📦 79

Code Quality 📦 28

Collaboration 📦 30

Command Line Interface 📦 48

Community 📦 81

Companies 📦 60

Compilers 📦 60

Computer Science 📦 74

Configuration Management 📦 39

Content Management 📦 167

Control Flow 📦 197

Data Formats 📦 77

Data Processing 📦 266

Data Storage 📦 132

Economics 📦 60

Frameworks 📦 198

Graphics 📦 103

Hardware 📦 148

Integrated Development Environments 📦 47

Learning Resources 📦 147

Libraries 📦 119

Lists Of Projects 📦 21

Machine Learning 📦 336

Mapping 📦 61

Marketing 📦 15

Mathematics 📦 55

Messaging 📦 97

Networking 📦 304

Operating Systems 📦 84

Operations 📦 120

Package Managers 📦 52

Programming Languages 📦 229

Runtime Environments 📦 96

Science 📦 42

Security 📦 375

Social Media 📦 26

Software Architecture 📦 70

Software Development 📦 68

Software Performance 📦 57

Software Quality 📦 127

Text Editors 📦 45

Text Processing 📦 131

User Interface 📦 310

User Interface Components 📦 465

Version Control 📦 29

Virtualization 📦 68

Web Browsers 📦 38

Web Servers 📦 25

Web User Interface 📦 194

The Top 6,925 Verilog Open Source Projects on Github

Categories > Hardware > Verilog

Platformio Core ⭐ 5,629

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Chisel3 ⭐ 2,365

Chisel 3: A Modern Hardware Design Language

Openwifi ⭐ 2,300

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

Logisim Evolution ⭐ 2,032

Digital logic design tool and simulator

Picorv32 ⭐ 1,867

PicoRV32 - A Size-Optimized RISC-V CPU

E200_opensource ⭐ 1,688

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Wujian100_open ⭐ 1,456

IC design and development should be faster，simpler and more reliable

Vexriscv ⭐ 1,412

A FPGA friendly 32 bit RISC-V CPU implementation

Darkriscv ⭐ 1,298

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Nyuziprocessor ⭐ 1,145

GPGPU microprocessor architecture

Icestudio ⭐ 1,110

❄️ Visual editor for open FPGA boards

Clash Compiler ⭐ 1,072

Haskell to VHDL/Verilog/SystemVerilog compiler

Verilator ⭐ 1,019

Verilator open-source SystemVerilog simulator and lint system

Verilog Ethernet ⭐ 963

Verilog Ethernet components for FPGA implementation

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Amiga2000 Gfxcard ⭐ 949

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

Metroboy ⭐ 944

A repository of gate-level simulators and tools for the original Game Boy.

Spinalhdl ⭐ 917

Scala based HDL

HDL libraries and projects

RTL, Cmodel, and testbench for NVDLA

Fusesoc ⭐ 787

Package manager and build abstraction tool for FPGA/ASIC development

Platformio Vscode Ide ⭐ 776

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

Corundum ⭐ 767

Open source, high performance, FPGA-based NIC

A small, light weight, RISC CPU soft core

Verilog library for ASIC and FPGA designers

SERV - The SErial RISC-V CPU

The USRP™ Hardware Driver Repository

Vtr Verilog To Routing ⭐ 603

Verilog to Routing -- Open Source CAD Flow for FPGA Research

An open source GPU based off of the AMD Southern Islands ISA.

Verilog2factorio ⭐ 561

This project will compile verilog (a hardware description language) into factorio blueprints.

Awesome Hdl ⭐ 518

Hardware Description Languages

Verilog Axi ⭐ 512

Verilog AXI components for FPGA implementation

Openlane ⭐ 500

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Platformio Atom Ide ⭐ 474

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

Microwatt ⭐ 473

A tiny Open POWER ISA softcore written in VHDL 2008

Openroad ⭐ 473

OpenROAD's unified application implementing an RTL-to-GDS Flow

🌱 Open source ecosystem for open FPGA boards

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Openc910 ⭐ 451

OpenXuantie - OpenC910 Core

Sd2snes ⭐ 432

SD card based multi-purpose cartridge for the SNES

Cascade ⭐ 416

A Just-In-Time Compiler for Verilog from VMware Research

Basic_verilog ⭐ 414

Must-have verilog systemverilog modules

Verilog Pcie ⭐ 393

Verilog PCI express components

Edalize ⭐ 376

An abstraction library for interfacing EDA tools

Riscv Formal ⭐ 373

RISC-V Formal Verification Framework

RISC-V CPU Core (RV32IM)

mor1kx - an OpenRISC 1000 processor IP core

Mips Cpu ⭐ 356

MIPS CPU implemented in Verilog

Open Fpga Verilog Tutorial ⭐ 355

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Ucr Eecs168 Lab ⭐ 346

The lab schedules for EECS168 at UC Riverside

Beagle_sdr_gps ⭐ 345

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

Openpiton ⭐ 345

The OpenPiton Platform

Odrivehardware ⭐ 335

High performance motor control

Verilogboy ⭐ 333

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

Graphics Gremlin ⭐ 328

Open source retro ISA video card

Openwifi Hw ⭐ 320

FPGA (chip) design of openwifi (IEEE 802.11)

Various HDL (Verilog) IP Cores

Biriscv ⭐ 300

32-bit Superscalar RISC-V CPU

Reduceron ⭐ 296

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

E203_hbirdv2 ⭐ 289

The Ultra-Low Power RISC-V Core

Step_into_mips ⭐ 271

一步一步写MIPS CPU

Fpga Imaging Library ⭐ 271

An open source library for image processing on FPGA.

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

Litepcie ⭐ 264

Small footprint and configurable PCIe core

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Wb2axip ⭐ 260

Bus bridges and other odds and ends

synthesiseable ieee 754 floating point library in verilog

Project Zipline ⭐ 251

Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

Netfpga ⭐ 250

NetFPGA 1G infrastructure and gateware

Verilog 6502 ⭐ 246

A Verilog HDL model of the MOS 6502 CPU

Opentimer ⭐ 243

A High-performance Timing Analysis Tool for VLSI Systems

Verilog ⭐ 243

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Basejump_stl ⭐ 233

BaseJump STL: A Standard Template Library for SystemVerilog

Fpga Litecoin Miner ⭐ 231

A litecoin scrypt miner implemented with FPGA on-chip memory.

Scamp Cpu ⭐ 228

A homebrew 16-bit CPU with a homebrew Unix-like-ish operating system.

Red Pitaya Notes ⭐ 227

Notes on the Red Pitaya Open Source Instrument

Piccolo ⭐ 227

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

SystemVerilog to Verilog conversion

SystemVerilog compiler and language services

Vscode Teroshdl ⭐ 212

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Sv Parser ⭐ 208

SystemVerilog parser library fully complient with IEEE 1800-2017

Verilog Generator Of Neural Net Digit Detector For Fpga ⭐ 206

Verilog Generator of Neural Net Digit Detector for FPGA

Verilog Practice ⭐ 205

HDLBits website practices & solutions

Open source implementation of a x86 processor

Verilog I2c ⭐ 194

Verilog I2C interface for FPGA implementation

FPGA,Verilog,Python,AI

Surelog ⭐ 193

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

The USRP™ Hardware Driver FPGA Repository

Apicula ⭐ 190

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Icesugar ⭐ 189

iCESugar FPGA Board (base on iCE40UP5k)

Ice40 Playground ⭐ 188

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

An open source SPI flash emulator and monitor

Convolution_network_on_fpga ⭐ 187

CNN acceleration on virtex-7 FPGA with verilog HDL

Ridecore ⭐ 185

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Scale Mamba ⭐ 183

Repository for the SCALE-MAMBA MPC system

SystemVerilog language server

1-100 of 6,925 projects

Related Projects

Verilog Fpga Projects (617)

Verilog Systemverilog Projects (173)

Verilog Vhdl Projects (144)

Verilog Cpu Projects (114)

Verilog Hdl Projects (114)

Python Verilog Projects (105)

Verilog Risc V Projects (102)

Verilog Rtl Projects (86)

C Verilog Projects (81)

Verilog Xilinx Projects (78)

Verilog Vhdl Fpga Projects (73)

Verilog Fpga Systemverilog Projects (70)

Verilog Vivado Projects (70)

Verilog Hardware Projects (68)

C Plus Plus Verilog Projects (60)

Verilog Fpga Hdl Projects (54)

Verilog Fpga Xilinx Projects (50)

Verilog Fpga Risc V Projects (47)

Verilog Fpga Rtl Projects (47)

Verilog Processor Projects (46)

Verilog Verilator Projects (45)

Verilog Hardware Fpga Projects (44)

Verilog Asic Projects (43)

Verilog Altera Projects (43)

C Verilog Fpga Projects (41)

Python Verilog Fpga Projects (41)

Verilog Simulation Projects (41)

Verilog Fpga Cpu Projects (38)

Verilog Fpga Vivado Projects (38)

Verilog Systemverilog Rtl Projects (37)

Verilog Uart Projects (36)

Verilog Ice40 Projects (36)

Verilog Fpga Asic Projects (34)

Python Verilog Systemverilog Projects (34)

Verilog Fpga Altera Projects (33)

Verilog Eda Projects (32)

Verilog Systemverilog Hdl Projects (30)

Verilog Cpu Risc V Projects (29)

Python Verilog Vhdl Projects (29)

Verilog Fpga Ice40 Projects (28)

Verilog Vhdl Systemverilog Projects (27)

Verilog Fpga Verilator Projects (26)

C Plus Plus Verilog Fpga Projects (26)

Verilog Vhdl Hdl Projects (26)

Verilog Yosys Projects (26)

Verilog Soc Projects (25)

Verilog Synthesis Projects (25)

Verilog Xilinx Vivado Projects (25)

Assembly Verilog Projects (23)

Verilog Icestorm Projects (23)

Verilog Fpga Uart Projects (23)

Python Verilog Hdl Projects (23)

Verilog Lattice Projects (22)

Verilog Vlsi Projects (22)

Verilog Usb Projects (22)

Verilog Fpga Lattice Projects (21)

Verilog Zynq Projects (20)

Verilog Fpga Icestorm Projects (20)

Verilog Systemverilog Asic Projects (20)

Javascript Verilog Projects (19)

Verilog Verification Projects (19)

Verilog Fpga Usb Projects (19)

Verilog Compiler Projects (18)

Verilog Tcl Projects (18)

Verilog Spi Projects (18)

Verilog Fpga Zynq Projects (17)

Verilog Fpga Xilinx Vivado Projects (17)

Verilog Fpga Processor Projects (17)

Verilog Fpga Systemverilog Asic Projects (16)

Verilog Uvm Projects (16)

Verilog Wishbone Projects (16)

Verilog Risc V Rv32i Projects (16)

Verilog Rv32i Projects (16)

Verilog Wishbone Bus Projects (15)

Scala Verilog Projects (15)

Java Verilog Projects (15)

Verilog Simulator Projects (15)

Verilog Fpga Soc Projects (15)

Linux Verilog Projects (14)

Verilog Artix 7 Projects (14)

Verilog Fpga Eda Projects (13)

Verilog Rtl Asic Projects (13)

Verilog Rtl Hdl Projects (13)

Verilog Chisel3 Projects (12)

Verilog Fpga Cpu Risc V Projects (12)

Haskell Verilog Projects (12)

Verilog Systemverilog Verilator Projects (12)

Hacktoberfest Verilog Projects (12)

Verilog Xilinx Altera Projects (12)

Open Source Verilog Projects (12)

Rust Verilog Projects (12)

Verilog Parser Projects (12)

Verilog Systemverilog Uvm Projects (12)

Verilog Chisel Projects (11)

Verilog Hardware Description Language Projects (11)

Python Verilog Vhdl Fpga Projects (11)

Verilog Microcontroller Projects (11)

Advertising 📦 9

Application Programming Interfaces 📦 120

Applications 📦 181

Artificial Intelligence 📦 72

Blockchain 📦 70

Build Tools 📦 111

Cloud Computing 📦 79

Code Quality 📦 28

Collaboration 📦 30

Command Line Interface 📦 48

Community 📦 81

Companies 📦 60

Compilers 📦 60

Computer Science 📦 74

Configuration Management 📦 39

Content Management 📦 167

Control Flow 📦 197

Data Formats 📦 77

Data Processing 📦 266

Data Storage 📦 132

Economics 📦 60

Frameworks 📦 198

Graphics 📦 103

Hardware 📦 148

Integrated Development Environments 📦 47

Learning Resources 📦 147

Libraries 📦 119

Lists Of Projects 📦 21

Machine Learning 📦 336

Mapping 📦 61

Marketing 📦 15

Mathematics 📦 55

Messaging 📦 97

Networking 📦 304

Operating Systems 📦 84

Operations 📦 120

Package Managers 📦 52

Programming Languages 📦 229

Runtime Environments 📦 96

Science 📦 42

Security 📦 375

Social Media 📦 26

Software Architecture 📦 70

Software Development 📦 68

Software Performance 📦 57

Software Quality 📦 127

Text Editors 📦 45

Text Processing 📦 131

User Interface 📦 310

User Interface Components 📦 465

Version Control 📦 29

Virtualization 📦 68

Web Browsers 📦 38

Web Servers 📦 25

Web User Interface 📦 194

"GitHub" is a registered trademark of GitHub, Inc. Awesome Open Source is not affiliated with GitHub.

All non readme contents or Github based topics or project metadata copyright Awesome Open Source 2018-2022