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The Top 5,323 Verilog Open Source Projects

Categories > Hardware > Verilog
Platformio Core ⭐ 6,539
A professional collaborative platform for embedded development 👽
total releases 16most recent commit 4 days ago
Logisim Evolution ⭐ 3,022
Digital logic design tool and simulator
most recent commit 2 days ago
Chisel3 ⭐ 2,893
Chisel 3: A Modern Hardware Design Language
dependent packages 8total releases 56most recent commit 19 hours ago
Digital ⭐ 2,829
A digital logic designer and circuit simulator.
most recent commit 7 days ago
Openwifi ⭐ 2,818
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
most recent commit 8 days ago
Yosys ⭐ 2,514
Yosys Open SYnthesis Suite
most recent commit a day ago
Iverilog ⭐ 2,067
Icarus Verilog
most recent commit 10 days ago
Picorv32 ⭐ 1,946
PicoRV32 - A Size-Optimized RISC-V CPU
most recent commit a year ago
Vexriscv ⭐ 1,773
A FPGA friendly 32 bit RISC-V CPU implementation
most recent commit 9 days ago
E200_opensource ⭐ 1,688
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
most recent commit 2 years ago
Fromthetransistor ⭐ 1,607
From the Transistor to the Web Browser, a rough outline for a 12 week course
most recent commit a year ago
Nyuziprocessor ⭐ 1,576
GPGPU microprocessor architecture
most recent commit 5 months ago
Darkriscv ⭐ 1,538
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
most recent commit a month ago
Verilator ⭐ 1,472
Verilator open-source SystemVerilog simulator and lint system
dependent packages 1total releases 6most recent commit a day ago
Wujian100_open ⭐ 1,456
IC design and development should be faster，simpler and more reliable
most recent commit a year ago
Icestudio ⭐ 1,433
❄️ Visual editor for open FPGA boards
most recent commit 14 days ago
Verilog Ethernet ⭐ 1,352
Verilog Ethernet components for FPGA implementation
most recent commit a day ago
Cocotb ⭐ 1,261
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
dependent packages 16total releases 36most recent commit a day agopypi cocotb} Downloads
Hw ⭐ 1,254
RTL, Cmodel, and testbench for NVDLA
most recent commit a year ago
Clash Compiler ⭐ 1,219
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 81most recent commit 2 days ago
Spinalhdl ⭐ 1,195
Scala based HDL
dependent packages 3total releases 126most recent commit 3 days ago
Fpga ⭐ 1,103
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
most recent commit 8 months ago
Circt ⭐ 1,103
Circuit IR Compilers and Tools
most recent commit a day ago
Hdl ⭐ 1,083
HDL libraries and projects
most recent commit 18 hours ago
Silice ⭐ 1,072
Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.
most recent commit 4 days ago
Metroboy ⭐ 1,017
A repository of gate-level simulators and tools for the original Game Boy.
most recent commit a month ago
Corundum ⭐ 1,008
Open source FPGA-based NIC and platform for in-network compute
most recent commit 2 months ago
Platformio Vscode Ide ⭐ 963
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
total releases 25most recent commit 17 days ago
Amiga2000 Gfxcard ⭐ 960
MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog
most recent commit a month ago
Zipcpu ⭐ 958
A small, light weight, RISC CPU soft core
most recent commit a month ago
Basic_verilog ⭐ 945
Must-have verilog systemverilog modules
most recent commit 2 days ago
Fusesoc ⭐ 913
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 2total releases 20most recent commit 8 days agopypi fusesoc} Downloads
Serv ⭐ 885
SERV - The SErial RISC-V CPU
most recent commit a month ago
Xls ⭐ 863
XLS: Accelerated HW Synthesis
most recent commit a day ago
Oh ⭐ 858
Verilog library for ASIC and FPGA designers
most recent commit 3 months ago
Openlane ⭐ 822
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
most recent commit a day ago
Verilog Axi ⭐ 777
Verilog AXI components for FPGA implementation
most recent commit 2 months ago
Vtr Verilog To Routing ⭐ 760
Verilog to Routing -- Open Source CAD Flow for FPGA Research
most recent commit 2 days ago
Chisel Bootcamp ⭐ 754
Generator Bootcamp Material: Learn Chisel the Right Way
most recent commit 7 days ago
Uhd ⭐ 747
The USRP™ Hardware Driver Repository
dependent packages 3total releases 9most recent commit 2 days ago
Bsc ⭐ 740
Bluespec Compiler (BSC)
most recent commit 3 days ago
Openc910 ⭐ 723
OpenXuantie - OpenC910 Core
most recent commit 21 days ago
Openroad ⭐ 719
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
most recent commit a day ago
Vortex ⭐ 710
most recent commit 2 days ago
Awesome Hdl ⭐ 668
Hardware Description Languages
most recent commit 2 days ago
Cello ⭐ 616
Genetic circuit design automation
most recent commit 2 years ago
Apio ⭐ 596
🌱 Open source ecosystem for open FPGA boards
total releases 141most recent commit 13 days ago
Minecrafthdl ⭐ 595
A Verilog synthesis flow for Minecraft redstone circuits
most recent commit 2 years ago
E203_hbirdv2 ⭐ 592
The Ultra-Low Power RISC-V Core
most recent commit 3 months ago
Miaow ⭐ 582
An open source GPU based off of the AMD Southern Islands ISA.
most recent commit 5 years ago
Verilog2factorio ⭐ 578
This project will compile verilog (a hardware description language) into factorio blueprints.
most recent commit 10 months ago
Verilog Pcie ⭐ 551
Verilog PCI express components
most recent commit 3 months ago
Riscv Sodor ⭐ 549
educational microarchitectures for risc-v isa
most recent commit 9 days ago
Openfpga ⭐ 534
An Open-source FPGA IP Generator
most recent commit a day ago
Microwatt ⭐ 522
A tiny Open POWER ISA softcore written in VHDL 2008
most recent commit 2 months ago
Riffa ⭐ 493
The RIFFA development repository
most recent commit 4 months ago
Scr1 ⭐ 489
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
most recent commit 9 months ago
Edalize ⭐ 486
An abstraction library for interfacing EDA tools
dependent packages 2total releases 19most recent commit 8 days agopypi edalize} Downloads
Platformio Atom Ide ⭐ 474
PlatformIO IDE for Atom: The next generation integrated development environment for IoT
most recent commit 2 years ago
Riscv_vhdl ⭐ 469
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
most recent commit 21 hours ago
Usb_c_industrial_camera_fpga_usb3 ⭐ 457
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
most recent commit 13 days ago
Corundum ⭐ 455
Open source, high performance, FPGA-based NIC
most recent commit 2 years ago
Openwifi Hw ⭐ 437
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
most recent commit 11 days ago
Hardcaml ⭐ 428
Hardcaml is an OCaml library for designing hardware.
most recent commit 2 months ago
Pyverilog ⭐ 422
Python-based Hardware Design Processing Toolkit for Verilog HDL
dependent packages 7total releases 24most recent commit a month agopypi pyverilog} Downloads
Hal ⭐ 422
HAL – The Hardware Analyzer
most recent commit 10 days ago
Ucr Eecs168 Lab ⭐ 421
The lab schedules for EECS168 at UC Riverside
most recent commit a day ago
Openpiton ⭐ 416
The OpenPiton Platform
most recent commit 3 months ago
Cascade ⭐ 416
A Just-In-Time Compiler for Verilog from VMware Research
most recent commit 2 years ago
8bitworkshop ⭐ 414
web-based IDE for 8-bit programming and Verilog development
most recent commit 2 months ago
Beagle_sdr_gps ⭐ 394
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
most recent commit 19 days ago
Projf Explore ⭐ 391
Project F brings FPGAs to life with exciting open-source designs you can build on.
most recent commit 4 days ago
Graphics Gremlin ⭐ 389
Open source retro ISA video card
most recent commit a month ago
Verilogboy ⭐ 388
A Pi emulating a GameBoy sounds cheap. What about an FPGA?
most recent commit 2 months ago
Mor1kx ⭐ 384
mor1kx - an OpenRISC 1000 processor IP core
most recent commit 8 months ago
Verilog Practice ⭐ 382
HDLBits website practices & solutions
most recent commit 2 months ago
Riscv Formal ⭐ 373
RISC-V Formal Verification Framework
most recent commit a year ago
Opentimer ⭐ 368
A High-performance Timing Analysis Tool for VLSI Systems
most recent commit 2 months ago
Riscv ⭐ 364
RISC-V CPU Core (RV32IM)
most recent commit a year ago
Mips Cpu ⭐ 356
MIPS CPU implemented in Verilog
most recent commit 5 years ago
Slang ⭐ 353
SystemVerilog compiler and language services
most recent commit 6 days ago
Litepcie ⭐ 343
Small footprint and configurable PCIe core
most recent commit 7 days ago
Cfu Playground ⭐ 339
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
most recent commit 5 days ago
Basejump_stl ⭐ 331
BaseJump STL: A Standard Template Library for SystemVerilog
most recent commit 20 hours ago
Leflow ⭐ 329
Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
most recent commit 3 years ago
Sv2v ⭐ 319
SystemVerilog to Verilog conversion
total releases 3most recent commit 19 days ago
Wb2axip ⭐ 316
Bus bridges and other odds and ends
most recent commit 2 months ago
Vscode Teroshdl ⭐ 314
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
most recent commit 16 days ago
Vroom ⭐ 304
VRoom! RISC-V CPU
most recent commit 5 days ago
Cores ⭐ 302
Various HDL (Verilog) IP Cores
most recent commit 2 years ago
Biriscv ⭐ 300
32-bit Superscalar RISC-V CPU
most recent commit a year ago
Flute ⭐ 297
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
most recent commit a month ago
Reduceron ⭐ 296
FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to
most recent commit 2 years ago
Svls ⭐ 293
SystemVerilog language server
total releases 36most recent commit 6 days ago
Sv Parser ⭐ 288
SystemVerilog parser library fully compliant with IEEE 1800-2017
dependent packages 4total releases 58most recent commit 2 months agocargo sv-parser-syntaxtree} Downloads
Apicula ⭐ 281
Project Apicula 🐝: bitstream documentation for Gowin FPGAs
dependent packages 1total releases 25most recent commit 5 days agopypi Apycula} Downloads
Verilog_systemverilog.vim ⭐ 279
Verilog/SystemVerilog Syntax and Omni-completion
most recent commit 2 months ago
Fpga Imaging Library ⭐ 271
An open source library for image processing on FPGA.
most recent commit 8 years ago
Step_into_mips ⭐ 271
一步一步写MIPS CPU
most recent commit a year ago
Icezum ⭐ 265
🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board
most recent commit 3 years ago
1-100 of 5,323 projects
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