Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Logisim Evolution | 4,251 | a month ago | 209 | gpl-3.0 | Java | |||||
Digital logic design tool and simulator | ||||||||||
Digital | 3,476 | 4 months ago | 87 | gpl-3.0 | Java | |||||
A digital logic designer and circuit simulator. | ||||||||||
Vexriscv | 2,135 | 4 months ago | 100 | mit | Assembly | |||||
A FPGA friendly 32 bit RISC-V CPU implementation | ||||||||||
Cocotb | 1,612 | 9 | 22 | 8 days ago | 44 | October 06, 2023 | 415 | bsd-3-clause | Python | |
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python | ||||||||||
Spinalhdl | 1,451 | 4 | 4 months ago | 140 | November 01, 2023 | 106 | other | Scala | ||
Scala based HDL | ||||||||||
Neorv32 | 1,337 | 4 months ago | 15 | bsd-3-clause | VHDL | |||||
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. | ||||||||||
Clash Compiler | 1,336 | 44 | 4 months ago | 87 | November 11, 2023 | 280 | other | Haskell | ||
Haskell to VHDL/Verilog/SystemVerilog compiler | ||||||||||
Fusesoc | 1,065 | 5 | 5 | 4 months ago | 26 | November 17, 2023 | 119 | bsd-2-clause | Python | |
Package manager and build abstraction tool for FPGA/ASIC development | ||||||||||
Awesome Hdl | 830 | 4 months ago | 1 | |||||||
Hardware Description Languages | ||||||||||
Microwatt | 634 | 4 months ago | 44 | other | Verilog | |||||
A tiny Open POWER ISA softcore written in VHDL 2008 |