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Search results for python vhdl
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vhdl
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81 search results found
Cocotb
⭐
1,583
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Fusesoc
⭐
1,065
Package manager and build abstraction tool for FPGA/ASIC development
Edalize
⭐
573
An abstraction library for interfacing EDA tools
Pipelinec
⭐
519
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Hal
⭐
490
HAL – The Hardware Analyzer
Awesome Open Hardware Verification
⭐
353
A List of Free and Open Source Hardware Verification Tools and Frameworks
Poc
⭐
324
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Surf
⭐
259
A huge VHDL library for FPGA development
Hdlconvertor
⭐
258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
Hwt
⭐
189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Vhdl Style Guide
⭐
159
Style guide enforcement for VHDL
Hdl_checker
⭐
136
Repurposing existing HDL tools to help writing better code
Image Processing
⭐
123
Image Processing Toolbox in Verilog using Basys3 FPGA
Symbolator
⭐
73
HDL symbol generator
Pyvhdlparser
⭐
69
Streaming based VHDL parser.
Msxpi
⭐
65
Interface for MSX to Connect and use Raspberry Pi resources
Simon_speck_ciphers
⭐
61
Implementations of the Simon and Speck Block Ciphers
Ipxact2systemverilog
⭐
55
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
Vim Hdl
⭐
53
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
Hdlparse
⭐
51
Simple parser for extracting VHDL documentation
Pyvhdlmodel
⭐
44
An abstract language model of VHDL written in Python.
Awesome Hwd Tools
⭐
41
A curated list of awesome open source hardware design tools
Vhdl Mode
⭐
36
A package for Sublime Text that aids coding in the VHDL language.
Conifer
⭐
35
Fast inference of Boosted Decision Trees in FPGAs
Hwtlib
⭐
33
hardware library for hwt (= ipcore repo)
Xeda
⭐
30
Cross EDA Abstraction and Automation
Hdlconvertorast
⭐
25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
Neorv32 Riscof
⭐
22
✔️Port of RISCOF to verify the NEORV32 Processor for RISC-V ISA compatibility.
Vhdlproc
⭐
20
VHDLproc is a VHDL preprocessor
Hwthls
⭐
20
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
Pythonuberhdl
⭐
20
Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL
Vhdldomain
⭐
18
A Sphinx domain providing VHDL language support.
Sphinx Vhdl
⭐
17
Vivado Ci
⭐
17
A simple Vivado (Verilog & VHDL) Continuous Integration tool with seamless integration to Travis-CI
Sdram_controller
⭐
16
Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)
Crcgen
⭐
16
Generator for CRC HDL code (VHDL, Verilog, MyHDL)
Psi_fix
⭐
15
Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
Pymips
⭐
15
A pipelined MIPS processor implemented in Python
Kpi Stuff
⭐
15
Some of my laboratories work in KPI and stuff connected with it.
Pyarch
⭐
14
🔌 Hardware Abstraction Library in Python
Aes Gcm 128 192 256 Bits
⭐
14
Configurable AES-GCM IP (128, 192, 256 bits)
Pyvhdl2sch
⭐
14
pyVhdl2sch is a python based VHDL to (pdf) schematic converter
Vhdl_gen
⭐
12
A VHDL generator made with Python
Myblaze
⭐
12
MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of MB-Lite from VHDL to MyHDL, along with a simple emulator. Its minimal configuration was tested on the Spartan-3E Starter Kit.
Cosim
⭐
11
Interfacing VHDL and foreign languages with VUnit
Opencores Scraper
⭐
11
few python scripts to clone all IP cores from opencores.org
Smartvhdl
⭐
11
SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)
Pyedaa.projectmodel
⭐
10
An abstract model of EDA tool projects.
Fpga_hw_sim_fwk_2
⭐
10
FPGA Hardware Simulation Framework
Teroshdl Documenter Demo
⭐
9
This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
Hdlgen Chatgpt
⭐
9
HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
Pocket Cnn
⭐
9
CNN-to-FPGA-framework for small CNN, written in VHDL and Python
Pyha
⭐
9
Describe, simulate and debug hardware in Python
Uaveiro Leci
⭐
9
Todo o trabalho feito ao longo do curso de LECI na Universidade de Aveiro
Fpga_hw_sim_fwk
⭐
8
FPGA Hardware Simulation Framework
Canopen Vhdl
⭐
8
A lightweight CANopen controller in VHDL
Vhdre
⭐
8
Generator for VHDL regular expression matchers
Slvcodec
⭐
8
Generate conversions to/from VHDL types and std_logic_vector. Generate python-based tests.
Myhdl Addons
⭐
8
MyHDL related subprojects
Sphinx Hwt
⭐
7
Sphinx extension for visual documentation of hardware written in HWT
Python Quartus
⭐
7
A python replacement for the Tcl interface to quartus
Randoms
⭐
7
Tinkering and Playing around!
Vhdmmio
⭐
7
VHDL code generator for AXI4-lite register files
Logidiff
⭐
7
A website and Python library for determining if two logical statements are equivalent. Uses VHDL syntax and logical operators.
Svmodule
⭐
6
SystemVerilog & Verilog Module I/O parser and printer
Decision_tree
⭐
6
Python program for training the decision tree for people detection (based on LBP - Local Binary Patterns) and converting the tree to hardware (FPGA) implementation.
Pyxhdl
⭐
6
Python Frontend For VHDL And Verilog
Bust
⭐
6
Utility for creating and modifying VHDL bus slave modules
Img_rom
⭐
6
Various scripts to create a VHDL or verilog ROM file from an image in PPM PGM or PBM format, also from a NES ROM, or a RISC-V dump memory file
Edapack
⭐
6
Provides a packaged collection of open source EDA tools
Pyvhdl
⭐
6
Initial 0.0.1 push
Ipcorepackager
⭐
6
Scriptable IP-Core generator
Yaaes
⭐
5
Yet Another AES implementation in hardware.
Bundle
⭐
5
FPGA-accelerated array computing
Vtags
⭐
5
Verdi like, verilog code signal trace and show hierarchy script
Wavedisp
⭐
5
Python classes to create agnostic wave files for HDL simulator viewer
Legohdl
⭐
5
An experimental package manager and development tool for Hardware Description Languages (HDL).
Sublimelinter Contrib Xsim
⭐
5
Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.
Autosub
⭐
5
Automatic Submission System for E-Learning
Ipxact
⭐
5
IPXACT to VHDL package and C header
Code Portfolio
⭐
5
Code Portfolio -- Collection of Interesting CS and ECE Projects in different languages (C, C++, Python, CPU & GPU Parallel Paradigms, MATLAB, and VHDL) and target hardware with technical reports, and my Vim Config
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