| logisim-evolution/logisim-evolution |
6,725 |
|
0 |
0 |
5 months ago |
0 |
|
209 |
gpl-3.0 |
Java |
| Digital logic design tool and simulator |
| hneemann/Digital |
3,476 |
|
0 |
0 |
over 2 years ago |
0 |
|
87 |
gpl-3.0 |
Java |
| A digital logic designer and circuit simulator. |
| SpinalHDL/VexRiscv |
2,135 |
|
0 |
0 |
over 2 years ago |
0 |
|
100 |
mit |
Assembly |
| A FPGA friendly 32 bit RISC-V CPU implementation |
| SpinalHDL/SpinalHDL |
1,912 |
|
0 |
4 |
5 months ago |
140 |
November 01, 2023 |
106 |
other |
Scala |
| Scala based HDL |
| cocotb/cocotb |
1,519 |
|
9 |
22 |
over 2 years ago |
44 |
October 06, 2023 |
415 |
bsd-3-clause |
Python |
| cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
| stnolting/neorv32 |
1,337 |
|
0 |
0 |
over 2 years ago |
0 |
|
15 |
bsd-3-clause |
VHDL |
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. |
| clash-lang/clash-compiler |
1,336 |
|
44 |
0 |
over 2 years ago |
87 |
November 11, 2023 |
280 |
other |
Haskell |
| Haskell to VHDL/Verilog/SystemVerilog compiler |
| olofk/fusesoc |
1,065 |
|
5 |
5 |
over 2 years ago |
26 |
November 17, 2023 |
119 |
bsd-2-clause |
Python |
| Package manager and build abstraction tool for FPGA/ASIC development |
| drom/awesome-hdl |
830 |
|
0 |
0 |
over 2 years ago |
0 |
|
1 |
|
|
| Hardware Description Languages |
| antonblanchard/microwatt |
634 |
|
0 |
0 |
over 2 years ago |
0 |
|
44 |
other |
Verilog |
| A tiny Open POWER ISA softcore written in VHDL 2008 |
