| olofk/fusesoc |
1,428 |
|
5 |
5 |
28 days ago |
26 |
November 17, 2023 |
119 |
bsd-2-clause |
Python |
| Package manager and build abstraction tool for FPGA/ASIC development |
| The-OpenROAD-Project/OpenROAD |
1,102 |
|
0 |
0 |
over 2 years ago |
0 |
|
282 |
bsd-3-clause |
Verilog |
| OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/ |
| verilog-to-routing/vtr-verilog-to-routing |
925 |
|
0 |
0 |
over 2 years ago |
0 |
|
447 |
other |
C++ |
| Verilog to Routing -- Open Source CAD Flow for FPGA Research |
| lnis-uofu/OpenFPGA |
692 |
|
0 |
0 |
over 2 years ago |
0 |
|
103 |
mit |
Verilog |
| An Open-source FPGA IP Generator |
| olofk/edalize |
573 |
|
2 |
3 |
over 2 years ago |
24 |
December 08, 2023 |
91 |
bsd-2-clause |
Python |
| An abstraction library for interfacing EDA tools |
| OpenTimer/OpenTimer |
368 |
|
0 |
0 |
over 3 years ago |
0 |
|
48 |
other |
Verilog |
| A High-performance Timing Analysis Tool for VLSI Systems |
| rggen/rggen |
261 |
|
0 |
0 |
over 2 years ago |
62 |
October 18, 2023 |
11 |
mit |
Ruby |
| Code generation tool for configuration and status registers |
| The-OpenROAD-Project/OpenROAD-flow-scripts |
233 |
|
0 |
0 |
over 2 years ago |
0 |
|
123 |
other |
Verilog |
| OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/ |
| SystemRDL/PeakRDL |
199 |
|
0 |
4 |
2 months ago |
11 |
October 26, 2023 |
2 |
lgpl-3.0 |
Python |
| Control and status register code generator toolchain |
| Juniper/open-register-design-tool |
169 |
|
0 |
0 |
almost 3 years ago |
0 |
|
23 |
apache-2.0 |
Verilog |
| Tool to generate register RTL, models, and docs using SystemRDL or JSpec input |
