RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
RgGen has following features:
RgGen is written in the Ruby programing language and its required version is 2.5 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see this page.
RgGen depends on following sub components and other Ruby libraries.
To install RgGen and the dependencies, use the command below:
$ gem install rggen
RgGen and dependencies will be installed on your system root.
If you want to install them on other location, you need to specify install path and set the
GEM_PATH environment variable:
$ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen $ export GEM_PATH=YOUR_INSTALL_DIRECTORY
You would get the following error message duaring installation if you have the old RgGen (version < 0.9).
ERROR: Error installing rggen: "rggen" from rggen-core conflicts with installed executable from rggen
To resolve the above error, there are three solutions. See this page
See Wiki documents.
plugin feature to allow your cusomization.
See this Wiki document for futher detals.
Following EDA tools can accept the generated source files.
You can get example configuration file and register map specification listed below:
By using these example files, you can try to use RgGen. Hit command below:
$ rggen -c config.yml -o out block_0.yml block_1.yml
-c: Specify path to your configuration file
-o: Specify path to the directory where generated files will be written to
Then, generated files listed below will be written to
See Contributing Guide.
Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
Everyone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the code of conduct.