|Project Name||Stars||Downloads||Repos Using This||Packages Using This||Most Recent Commit||Total Releases||Latest Release||Open Issues||License||Language|
|Darkriscv||1,719||14 days ago||15||bsd-3-clause||Verilog|
|opensouce RISC-V cpu core implemented in Verilog from scratch in one night!|
|Pipelinec||480||2 days ago||81||gpl-3.0||Python|
|A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.|
|Siafpgaminer||44||6 years ago||1||mit||VHDL|
|VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin|
|Mips Pipeline Simulator||15||a year ago||2||mit||Python|
|A MIPS Simulator with a 5-stage pipeline.|
|Mips||2||4 years ago||Verilog|
|MIPS CPU for ICS II|
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Please feel free to message - very happy to make PipelineC work for you! Always looking for help as well. -Julian
Get started by reading the wiki.
A C-like(1) hardware description language (HDL)(2) adding high level synthesis(HLS)-like automatic pipelining(3) as a language construct/compiler feature.
An easy to understand hardware description language with a powerful autopipelining compiler and growing set of real life hardware design inspired features.
Fundamental design elements are state machines/stateful elements(registers, rams, etc), auto-pipelined stateless pure functions, and interconnects (wires,cdc,async fifos,etc). Designs can be structured to look like 'communicating sequential processes/threads' as needed.
By isolating complex logic into autopipelineable functions, and only writing literal clock by clock hardware description when absolutely necessary, PipelineC designs do not need to be rewritten for each new target device / operating frequency. The hope is to build shared, high performance, device agnostic, hardware designs described in a familiar and powerfully composable C language look.
For software folks writing PipelineC should feel like solving a programming puzzle in C - the rules of the puzzle hide/imply hardware concepts. For hardware folks PipelineC is a better hardware description language trying to find middle ground between traditional RTL and HLS. It is my language of choice as an FPGA engineer :).