Pipelinec
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
| Pipelinec | 519 | 3 months ago | 82 | gpl-3.0 | Python | |||||
| A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. | ||||||||||
| Siafpgaminer | 44 | 6 years ago | 1 | mit | VHDL | |||||
| VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin | ||||||||||
| Mips Pipeline Simulator | 15 | 2 years ago | 2 | mit | Python | |||||
| A MIPS Simulator with a 5-stage pipeline. | ||||||||||
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Python
C
Language
Pipeline
Clock
Fpga
Synthesis
Vhdl
Hls