Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Systemc Compiler | 205 | 3 months ago | 8 | other | C++ | |||||
This tool translates synthesizable SystemC code to synthesizable SystemVerilog. | ||||||||||
Scalehls | 157 | 9 months ago | 26 | other | MLIR | |||||
A scalable High-Level Synthesis framework on MLIR | ||||||||||
Llvm 9.0 Learner Tutorial | 82 | 2 years ago | gpl-3.0 | C++ | ||||||
A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it. | ||||||||||
Autosa | 80 | 2 years ago | 3 | mit | C++ | |||||
AutoSA: Polyhedral-Based Systolic Array Compiler | ||||||||||
Iroha | 30 | 3 years ago | bsd-3-clause | C++ | ||||||
Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS) | ||||||||||
Hwthls | 20 | a year ago | mit | Python | ||||||
LLVM based HLS library for HWToolkit (hardware devel. toolkit) | ||||||||||
Comba | 19 | 4 years ago | 1 | gpl-3.0 | C++ | |||||
A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications | ||||||||||
C Ll Verilog | 10 | 7 years ago | mit | C++ | ||||||
An LLVM based mini-C to Verilog High-level Synthesis tool |