Xeda
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Openroad | 1,102 | 3 months ago | 282 | bsd-3-clause | Verilog | |||||
| OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/ | ||||||||||
| Fusesoc | 1,065 |  | 5 | 5 | 3 months ago | 26 | November 17, 2023 | 119 | bsd-2-clause | Python |
| Package manager and build abstraction tool for FPGA/ASIC development | ||||||||||
| Vtr Verilog To Routing | 925 | 3 months ago | 447 | other | C++ | |||||
| Verilog to Routing -- Open Source CAD Flow for FPGA Research | ||||||||||
| Openfpga | 692 | 3 months ago | 103 | mit | Verilog | |||||
| An Open-source FPGA IP Generator | ||||||||||
| Edalize | 573 |  | 2 | 3 | 3 months ago | 24 | December 08, 2023 | 91 | bsd-2-clause | Python |
| An abstraction library for interfacing EDA tools | ||||||||||
| Opentimer | 368 | a year ago | 48 | other | Verilog | |||||
| A High-performance Timing Analysis Tool for VLSI Systems | ||||||||||
| Rggen | 261 | 3 months ago | 62 | October 18, 2023 | 11 | mit | Ruby | |||
| Code generation tool for configuration and status registers | ||||||||||
| Openroad Flow Scripts | 233 | 3 months ago | 123 | other | Verilog | |||||
| OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/ | ||||||||||
| Open Register Design Tool | 169 | 9 months ago | 23 | apache-2.0 | Verilog | |||||
| Tool to generate register RTL, models, and docs using SystemRDL or JSpec input | ||||||||||
| Vsdflow | 121 | a year ago | 5 | apache-2.0 | Verilog | |||||
| VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic. | ||||||||||
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