Rules_vivado
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Xls | 1,087 | 3 months ago | 607 | apache-2.0 | C++ | |||||
| XLS: Accelerated HW Synthesis | ||||||||||
| Bazel_rules_hdl | 90 | 3 months ago | 66 | apache-2.0 | Starlark | |||||
| Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build) | ||||||||||
| Rules_verilator | 16 | 2 years ago | apache-2.0 | Starlark | ||||||
| Bazel build rules for Verilator | ||||||||||
| Rules_vivado | 11 | 2 years ago | 4 | mit | Python | |||||
| Bazel rules for Xilinx Vivado | ||||||||||
| Ncore | 6 | 4 years ago | other | C++ | ||||||
| A RISCV processor in system verilog | ||||||||||
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Bazel Rules