Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Cocotb | 1,612 | 9 | 22 | 10 days ago | 44 | October 06, 2023 | 415 | bsd-3-clause | Python | |
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python | ||||||||||
Scr1 | 688 | 8 months ago | 3 | other | SystemVerilog | |||||
SCR1 is a high-quality open-source RISC-V MCU core in Verilog | ||||||||||
Sv2v | 429 | 4 months ago | 4 | June 22, 2023 | 22 | bsd-3-clause | Haskell | |||
SystemVerilog to Verilog conversion | ||||||||||
Leflow | 329 | 4 years ago | 1 | other | Verilog | |||||
Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks | ||||||||||
Nngen | 281 | 7 months ago | 5 | September 12, 2023 | 31 | apache-2.0 | Python | |||
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network | ||||||||||
Veriloggen | 275 | 1 | 8 months ago | 75 | September 12, 2023 | 19 | apache-2.0 | Python | ||
Veriloggen: A Mixed-Paradigm Hardware Construction Framework | ||||||||||
Fpu | 257 | 2 years ago | 13 | mit | Verilog | |||||
synthesiseable ieee 754 floating point library in verilog | ||||||||||
Verilog Mode | 231 | 4 months ago | 46 | gpl-3.0 | SystemVerilog | |||||
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org. | ||||||||||
Riscv Bitmanip | 174 | a year ago | 44 | cc-by-4.0 | Makefile | |||||
Working draft of the proposed RISC-V Bitmanipulation extension | ||||||||||
Iob Soc | 131 | 4 months ago | 8 | mit | Verilog | |||||
RISC-V System on Chip Template |