Project Name	Stars	Repos Using This	Packages Using This	Most Recent Commit	Total Releases	Latest Release	Open Issues	License	Language
Cocotb	1,583	9	22	10 days ago	44	October 06, 2023	415	bsd-3-clause	Python
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Scr1	688			7 months ago			3	other	SystemVerilog
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Sv2v	429			3 months ago	4	June 22, 2023	22	bsd-3-clause	Haskell
SystemVerilog to Verilog conversion
Leflow	329			4 years ago			1	other	Verilog
Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
Nngen	281			6 months ago	5	September 12, 2023	31	apache-2.0	Python
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
Veriloggen	275	1		7 months ago	75	September 12, 2023	19	apache-2.0	Python
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
Fpu	257			2 years ago			13	mit	Verilog
synthesiseable ieee 754 floating point library in verilog
Verilog Mode	231			3 months ago			46	gpl-3.0	SystemVerilog
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
Riscv Bitmanip	174			a year ago			44	cc-by-4.0	Makefile
Working draft of the proposed RISC-V Bitmanipulation extension
Iob Soc	131			3 months ago			8	mit	Verilog
RISC-V System on Chip Template

Alternatives To Sv2v

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Cocotb ⭐ 1,583

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

dependent packages 22total releases 44most recent commit 10 days ago

Scr1 ⭐ 688

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

most recent commit 7 months ago

Sv2v ⭐ 429

SystemVerilog to Verilog conversion

total releases 4most recent commit 3 months ago

Leflow ⭐ 329

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

most recent commit 4 years ago

Nngen ⭐ 281

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

total releases 5most recent commit 6 months ago

Veriloggen ⭐ 275

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

total releases 75most recent commit 7 months ago

Fpu ⭐ 257

synthesiseable ieee 754 floating point library in verilog

most recent commit 2 years ago

Verilog Mode ⭐ 231

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

most recent commit 3 months ago

Riscv Bitmanip ⭐ 174

Working draft of the proposed RISC-V Bitmanipulation extension

most recent commit a year ago

Iob Soc ⭐ 131

RISC-V System on Chip Template

most recent commit 3 months ago

Suggest An Alternative To sv2v

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