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Basic Simd Processor Verilog Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
Stars
41
License
gpl-3.0
Open Issues
3
Most Recent Commit
2 years ago
Programming Language
Verilog
Categories
Repo
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