| enjoy-digital/litex |
2,546 |
|
0 |
0 |
over 2 years ago |
0 |
|
239 |
other |
C |
| Build your hardware, easily! |
| SpinalHDL/VexRiscv |
2,135 |
|
0 |
0 |
over 2 years ago |
0 |
|
100 |
mit |
Assembly |
| A FPGA friendly 32 bit RISC-V CPU implementation |
| openhwgroup/cva6 |
1,946 |
|
0 |
0 |
over 2 years ago |
0 |
|
157 |
other |
Assembly |
| The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux |
| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| SI-RISCV/e200_opensource |
1,688 |
|
0 |
0 |
about 5 years ago |
0 |
|
33 |
apache-2.0 |
Verilog |
| Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 |
| stnolting/neorv32 |
1,337 |
|
0 |
0 |
over 2 years ago |
0 |
|
15 |
bsd-3-clause |
VHDL |
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. |
| ZipCPU/zipcpu |
1,139 |
|
0 |
0 |
over 2 years ago |
0 |
|
4 |
|
Verilog |
| A small, light weight, RISC CPU soft core |
| beehive-lab/TornadoVM |
1,054 |
|
0 |
0 |
over 2 years ago |
0 |
|
21 |
apache-2.0 |
Java |
| TornadoVM: A practical and efficient heterogeneous programming framework for managed languages |
| oneapi-src/oneAPI-samples |
758 |
|
0 |
0 |
over 2 years ago |
0 |
|
61 |
mit |
C++ |
| Samples for Intel® oneAPI Toolkits |
| riscv-mcu/e203_hbirdv2 |
741 |
|
0 |
0 |
about 3 years ago |
0 |
|
10 |
apache-2.0 |
Verilog |
| The Ultra-Low Power RISC-V Core |
