Cpu
A very primitive but hopefully self-educational CPU in Verilog
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Ao486_mister | 223 | 5 months ago | 46 | other | Verilog | |||||
| ao486 port for MiSTer | ||||||||||
| Cpu | 73 | 9 years ago | Verilog | |||||||
| A very primitive but hopefully self-educational CPU in Verilog | ||||||||||
| Up5k | 53 | 3 years ago | 1 | Verilog | ||||||
| Upduino v2 with the ice40 up5k FPGA demos | ||||||||||
| Dbgbus | 31 | 3 months ago | Verilog | |||||||
| A collection of debugging busses developed and presented at zipcpu.com | ||||||||||
| Mistery | 30 | 7 months ago | 2 | Verilog | ||||||
| Atari ST/STe core for FPGAs | ||||||||||
| Vim Verilog Instance | 22 | a year ago | 2 | mit | Python | |||||
| verilog_instance.vim: create instantiation of ports from port declaration | ||||||||||
| Hardcaml_of_verilog | 15 | 5 months ago | mit | OCaml | ||||||
| Convert Verilog to a Hardcaml design | ||||||||||
| Systemc Tutorial | 11 | 5 years ago | mit | C++ | ||||||
| Brief SystemC getting started tutorial | ||||||||||
| Panog2_nes | 8 | 2 years ago | Verilog | |||||||
| Port of Brian Bennet's NES Emulator for the second generation Panologic thin client | ||||||||||
| Hardcaml Yosys | 8 | 5 years ago | 3 | isc | Shell | |||||
| [DEPRECATED] Import verilog designs into hardcaml using yosys | ||||||||||
Alternatives To CpuSelect To Compare
Alternative Project Comparisons
Popular Verilog Projects
Popular Port Projects
Popular Hardware Categories
Get A Weekly Email With Trending Projects For These Categories
No Spam. Unsubscribe easily at any time.
Port
Cpu
Verilog