Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
Spinalhdl | 1,451 | 4 | 3 months ago | 140 | November 01, 2023 | 106 | other | Scala | ||
Scala based HDL | ||||||||||
Axi | 834 | 4 months ago | 49 | other | SystemVerilog | |||||
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication | ||||||||||
Firesim | 778 | 3 months ago | 218 | other | Scala | |||||
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility | ||||||||||
Cores Veer Eh1 | 770 | a year ago | 14 | apache-2.0 | SystemVerilog | |||||
VeeR EH1 core | ||||||||||
Openwifi Hw | 560 | 5 months ago | 5 | agpl-3.0 | Verilog | |||||
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware | ||||||||||
Riscv_vhdl | 552 | 4 months ago | 2 | apache-2.0 | Verilog | |||||
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators | ||||||||||
Nontrivial Mips | 362 | 4 years ago | other | SystemVerilog | ||||||
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux. | ||||||||||
Deepfloat | 333 | 5 years ago | 3 | other | SystemVerilog | |||||
An exploration of log domain "alternative floating point" for hardware ML/AI accelerators. | ||||||||||
Cores | 302 | 3 years ago | 3 | Verilog | ||||||
Various HDL (Verilog) IP Cores |