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141 search results found

Openwifi ⭐ 3,363

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Verilog Ethernet ⭐ 1,768

Verilog Ethernet components for FPGA implementation

Corundum ⭐ 1,354

Open source FPGA-based NIC and platform for in-network compute

Basic_verilog ⭐ 1,333

Must-have verilog systemverilog modules

HDL libraries and projects

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Edalize ⭐ 573

An abstraction library for interfacing EDA tools

Hardcaml ⭐ 571

Hardcaml is an OCaml library for designing hardware.

Openwifi Hw ⭐ 560

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Wb2axip ⭐ 409

Bus bridges and other odds and ends

Biriscv ⭐ 300

32-bit Superscalar RISC-V CPU

Fpga_readings ⭐ 249

Recipe for FPGA cooking

The USRP™ Hardware Driver FPGA Repository

Libsystemctlm Soc ⭐ 175

SystemC/TLM-2.0 Co-simulation framework

Awesome Fpga ⭐ 150

A collection of resources on FPGA devices and development in general

Fpga Sdcard Reader ⭐ 142

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

Hdl_checker ⭐ 136

Repurposing existing HDL tools to help writing better code

Usb3_pipe ⭐ 126

USB3 PIPE interface for Xilinx 7-Series

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Tinytpu ⭐ 111

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https://people.inf.ethz.ch/omutlu/pub/softMC_hpca

Panologic G2 ⭐ 96

Pano Logic G2 Reverse Engineering Project

2 hour crash course in FPGAs

Yosys F4pga Plugins ⭐ 81

Plugins for Yosys developed as part of the F4PGA project.

Xilinx Serial Miner ⭐ 75

Bitcoin miner for Xilinx FPGAs

Mipsfpga Plus ⭐ 74

MIPSfpga+ allows loading programs via UART and has a switchable clock

A Full Hardware Real-Time Ray-Tracer

Core_ddr3_controller ⭐ 69

A DDR3 memory controller in Verilog for various FPGAs

Tinyfpga_bx_usbserial ⭐ 63

USB Serial on the TinyFPGA BX

Sega System For Fpga ⭐ 61

FPGA Sega in Verilog, for Xilinx Virtex, circa 2002. Has an emulator thrown in, to simplify FPGA debugging.

Zynq Axis ⭐ 61

Hardware, Linux Driver and Library for the Zynq AXI DMA interface

Oc Accel ⭐ 58

OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Fpga Sdcard Reader Spi ⭐ 52

An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。

Verilog Projects ⭐ 49

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

Neorv32 Setups ⭐ 44

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.

Spi_mem_programmer ⭐ 41

Small (Q)SPI flash memory programmer in Verilog

Test of the USB3 IP Core from Daisho on a Xilinx device

A port of Linux to the OWON SDS7102 scope

Hyperram ⭐ 39

Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC

Xpm_vhdl ⭐ 38

A translation of the Xilinx XPM library to VHDL for simulation purposes

Brianhg Ddr3 Controller ⭐ 34

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Panologic ⭐ 34

PanoLogic Zero Client G1 reverse engineering info

hardware library for hwt (= ipcore repo)

Fpga_ntp_server ⭐ 32

A FPGA implementation of the NTP and NTS protocols

LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled

Verilog 2001 implementation of the ChaCha stream cipher.

Cnn_hardware_acclerator_for_fpga ⭐ 32

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

Fp23fftk ⭐ 31

Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

Arm Legv8 ⭐ 29

Verilog Implementation of an ARM LEGv8 CPU

Hedgehog Fused Spiking Neural Network Emulator Compute Engine ⭐ 29

HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.

Custom_part_data_files ⭐ 28

Xilinx PCIe to MIG DDR4 example designs and custom part data files

Xilinx Risc V ⭐ 26

Porting PicoRV32 to Artix-7 and Spartan-7. Generic vivado template for supported Xilinx FPGA is included.

mirror of https://git.elphel.com/Elphel/x393

Displayport ⭐ 25

DisplayPort IP-core

Open-source CSI-2 receiver for Xilinx UltraScale parts

A simple implementation of a UART modem in Verilog.

Hust Verilog Course ⭐ 25

华中科技大学计算机学院 Verilog 语言课程

Hwac_object_tracker ⭐ 24

FPGA accelerated TinyYOLO v2 object detection neural network

Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!

mirror of https://git.elphel.com/Elphel/eddr3

Scoreboard Wtimer ⭐ 23

Objective of this project was to emulate a Basketball scoreboard, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado.

My Verilog Examples ⭐ 22

A place to keep my synthesizable verilog examples.

Openhbmc ⭐ 21

Open-source high performance AXI4-based HyperRAM memory controller

Fpga Docker ⭐ 20

Tools for running FPGA vendor toolchains with Docker

Picorv32_xilinx ⭐ 19

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

Verilog Fpga ⭐ 19

Many peripherals in Verilog ready to use

Vloghammer ⭐ 19

A Verilog Synthesis Regression Test

Picoblaze Library ⭐ 18

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

Generic FIFO implementation with optional FWFT

Virtio implementation in SystemVerilog

Nfmac10g ⭐ 17

Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC

X393_sata ⭐ 15

mirror of https://git.elphel.com/Elphel/x393_sata

Vdt Plugin ⭐ 15

mirror of https://git.elphel.com/Elphel/vdt-plugin

Sha256hasher ⭐ 15

SHA-256 IP core for ZedBoard (Zynq SoC)

Deep Darkfantasy ⭐ 15

Global Dark Mode for ALL apps on ANY platforms.

Anasymod ⭐ 14

A framework for FPGA emulation of mixed-signal systems

Netfpga 10g Upb Openflow ⭐ 13

An OpenFlow implementation for the NetFPGA-10G card

Automatically Generate Wallace Tree Veriloghdl Code ⭐ 13

本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述

Nanorv32 ⭐ 13

A small 32-bit implementation of the RISC-V architecture

Pqriscv Vexriscv ⭐ 13

VexRiscv reference platforms for the pqriscv project

Implementation of the CMAC keyed hash function using AES as block cipher.

Hdl Deflate ⭐ 12

FPGA implementation of deflate (de)compress RFC 1950/1951

Awesome Fpga List ⭐ 12

A collection of some awesome public FPGA projects.

Study Materials ⭐ 12

Digital Design ⭐ 11

An introduction to integrated circuit design with Verilog and the Papilio Pro development board.

Zynq Aes ⭐ 11

AES hardware engine for Xilinx Zynq platform

Digital Hardware Modelling ⭐ 11

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

Core_usb_bridge ⭐ 11

USB -> AXI Debug Bridge

Rules_vivado ⭐ 11

Bazel rules for Xilinx Vivado

Kintex 7 Ov13850 Verilog ⭐ 10

kintex7 ov13850 fpga mipi camera

Verilog Fir ⭐ 9

FIR implemention with Verilog

Mechatronics Firmware ⭐ 9

mechatronics firmware

StarGate is a programming and runtime framework for enabing easy and efficient deployment of various accerators.

C64 Dodgypla ⭐ 9

Commodore 64 PLA replacement

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