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Search results for fpga xilinx
fpga
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295 search results found
Openwifi
⭐
3,363
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Aws Fpga
⭐
1,366
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
Corundum
⭐
1,354
Open source FPGA-based NIC and platform for in-network compute
Basic_verilog
⭐
1,333
Must-have verilog systemverilog modules
Hdl
⭐
1,299
HDL libraries and projects
Fpga
⭐
1,103
帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目
Brevitas
⭐
1,015
Brevitas: neural network quantization in PyTorch
Vitis Tutorials
⭐
972
Vitis In-Depth Tutorials
Openfpgaloader
⭐
948
Universal utility for programming FPGA
Pipecnn
⭐
916
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Hdmi
⭐
892
Send video/audio over HDMI on an FPGA
Prjxray
⭐
731
Documenting the Xilinx 7-series bit-stream format.
Vivado Risc V
⭐
682
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
S6_pcie_microblaze
⭐
642
PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info
Yolov2_xilinx_fpga
⭐
624
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard
Nmigen
⭐
589
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
Edalize
⭐
573
An abstraction library for interfacing EDA tools
Openwifi Hw
⭐
560
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Nvc
⭐
554
VHDL compiler and simulator
Xrt
⭐
491
Run Time for AIE and FPGA based platforms
Trisycl
⭐
424
Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group
Wb2axip
⭐
409
Bus bridges and other odds and ends
F32c
⭐
390
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
Nontrivial Mips
⭐
362
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Poc
⭐
324
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Vivado Boards
⭐
312
Sdaccel_examples
⭐
302
SDAccel Examples
Biriscv
⭐
300
32-bit Superscalar RISC-V CPU
Rapidwright
⭐
262
Build Customized FPGA Implementations for Vivado
Fpga_readings
⭐
249
Recipe for FPGA cooking
Hlslib
⭐
236
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Nitefury And Litefury
⭐
212
Public repository for Litefury & Nitefury
Xilinx_axidma
⭐
194
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
Fpga
⭐
192
The USRP™ Hardware Driver FPGA Repository
Gemm_hls
⭐
184
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
Guinness
⭐
172
GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA
Accelerating Cnn With Fpga
⭐
164
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
Xilinx Fpga Pcie Xdma Tutorial
⭐
150
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
Awesome Fpga
⭐
150
A collection of resources on FPGA devices and development in general
Fpga Sdcard Reader
⭐
142
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。
Fpga_as_a_service
⭐
139
Fpga Soc Linux
⭐
135
FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc:de10-nano)
Pcie_screamer
⭐
131
PCIe Screamer - TLPs experiments...
Jetson Rdma Picoevb
⭐
131
Minimal HW-based demo of GPUDirect RDMA on NVIDIA Jetson AGX Xavier running L4T
Rosetta
⭐
127
Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
Usb3_pipe
⭐
126
USB3 PIPE interface for Xilinx 7-Series
Logic
⭐
121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Hdmilight V2
⭐
119
HDMI Light v2 - FPGA based Ambilight clone with direct HDMI input
Litesata
⭐
118
Small footprint and configurable SATA core
Zynqmp Fpga Linux
⭐
114
FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
Tinytpu
⭐
111
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
W11
⭐
109
PDP-11/70 CPU core and SoC
Hls_tutorial_examples
⭐
107
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
Spinalhdl_cnn_accelerator
⭐
103
CNN accelerator implemented with Spinal HDL
Softmc
⭐
103
SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https://people.inf.ethz.ch/omutlu/pub/softMC_hpca
Pp4fpgas Cn Hls
⭐
102
HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn
Sycl
⭐
98
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
Panologic G2
⭐
96
Pano Logic G2 Reverse Engineering Project
Autobridge
⭐
94
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
Thundergp
⭐
90
HLS-based Graph Processing Framework on FPGAs
Fpga Shells
⭐
86
Xvcd
⭐
84
Xilinx Virtual Cable Daemon
Autobridge
⭐
81
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
Yosys F4pga Plugins
⭐
81
Plugins for Yosys developed as part of the F4PGA project.
Greta
⭐
76
GRETA expansion board for the Amiga 500 computer with Fast RAM, microSD mass storage and Ethernet controller, powered by FPGA technology.
Xilinx Serial Miner
⭐
75
Bitcoin miner for Xilinx FPGAs
Multizone Sdk
⭐
74
MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn't define TrustZone-like primitives to provide hardware separation. To shield critical functionality from untrusted third-party components, MultiZone provides hardware-enforced, software-defined separation of multi
Mipsfpga Plus
⭐
74
MIPSfpga+ allows loading programs via UART and has a switchable clock
Rt
⭐
71
A Full Hardware Real-Time Ray-Tracer
Libfpgalink
⭐
71
LIB:Library for interacting with an FPGA over USB
Shuhai
⭐
71
Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA
Core_ddr3_controller
⭐
69
A DDR3 memory controller in Verilog for various FPGAs
Tinyfpga_bx_usbserial
⭐
63
USB Serial on the TinyFPGA BX
Json For Vhdl
⭐
61
A JSON library implemented in VHDL.
Sega System For Fpga
⭐
61
FPGA Sega in Verilog, for Xilinx Virtex, circa 2002. Has an emulator thrown in, to simplify FPGA debugging.
Zynq Xdma
⭐
60
Linux Driver for the Zynq FPGA DMA engine
Vivado Build System
⭐
58
Vivado build system
Oc Accel
⭐
58
OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
Vivado_setup
⭐
57
How to set up Xilinx Vivado for source control
Intfftk
⭐
56
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Q27
⭐
53
27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting
Fpga Sdcard Reader Spi
⭐
52
An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线),可以从FAT16或FAT32格式的SD卡中读取文件。
Prjxray Db
⭐
51
Project X-Ray Database: XC7 Series
Pynq_composable_pipeline
⭐
48
PYNQ Composabe Overlays
Bigpulp
⭐
48
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
Ixo Usb Jtag
⭐
47
usb-jtag - Altera USB Blaster Emulation with a FX2
Ripple Fpga
⭐
47
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
Flexcnn
⭐
47
Dnn Accelerator
⭐
45
A DNN Accelerator implemented with RTL.
Clash Spaceinvaders
⭐
45
Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH
Rigel
⭐
44
Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
Neorv32 Setups
⭐
44
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
Bscan_spi_bitstreams
⭐
44
FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
Zynq Sandbox
⭐
41
a playground for xilinx zynq fpga experiments
Xup_compute_acceleration
⭐
41
Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
Dsitx
⭐
40
MIPI DSI transmitter core for Xilinx FPGAs (work in progress)
Daisho
⭐
40
Test of the USB3 IP Core from Daisho on a Xilinx device
Gemx
⭐
39
Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
Hyperram
⭐
39
Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
Sds7102
⭐
39
A port of Linux to the OWON SDS7102 scope
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