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Search results for fpga systemverilog
fpga
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systemverilog
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132 search results found
Clash Compiler
⭐
1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
Hdmi
⭐
892
Send video/audio over HDMI on an FPGA
Axi
⭐
834
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Edalize
⭐
573
An abstraction library for interfacing EDA tools
Pcileech Fpga
⭐
525
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
Projf Explore
⭐
478
Project F brings FPGAs to life with exciting open-source designs you can build on.
Vscode Teroshdl
⭐
457
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Nontrivial Mips
⭐
362
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Deepfloat
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333
An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
Fpga Foc
⭐
319
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器,用于驱动BLDC/PMSM电机。
Rggen
⭐
261
Code generation tool for configuration and status registers
Ustc Rvsoc
⭐
261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。
Hdlconvertor
⭐
258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
80x86
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222
80186 compatible SystemVerilog CPU core and FPGA reference design
Nitefury And Litefury
⭐
212
Public repository for Litefury & Nitefury
Hwt
⭐
189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Fpga Ftdi245fifo
⭐
178
FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。
Open Register Design Tool
⭐
169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Openfpga Nes
⭐
157
NES for the Analogue Pocket
Fpga Sdcard Reader
⭐
142
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。
Fpga Jpeg Ls Encoder
⭐
141
An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器,可实现高压缩率的无损/近无损图像压缩。
Coyote
⭐
137
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
Eurorack Pmod
⭐
137
Hardware and gateware for getting started in FPGA-based audio synthesis with open source tools.
Logic
⭐
121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Fpga Can
⭐
121
An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
Intel Fpga Bbb
⭐
101
Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
Fpga Application Development And Simulation
⭐
96
《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
Fpga Partial Reconfig
⭐
84
Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
Cheshire
⭐
80
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Hero
⭐
77
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
Fpga Nfc
⭐
73
Build an NFC (RFID) card reader using FPGA and simple circuit instead of RFID-specfic chip. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器,不需要专门的RFID芯片。
Shuhai
⭐
71
Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA
Analogue Pocket Utils
⭐
71
Collection of IP and information on how to develop for openFPGA and Analogue Pocket
Superscalar Riscv Cpu
⭐
69
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
Fpga Sdfake
⭐
69
Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。
Open Nic Shell
⭐
67
AMD OpenNIC Shell includes the HDL source files
Uh Jls
⭐
61
FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器,用来进行无损图像压缩。
Fpga Png Decoder
⭐
57
An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图象解码器,可以从PNG文件中解码出原始像素。
Zcash Fpga
⭐
57
Zcash FPGA acceleration engine
Fpga Mpeg2 Encoder
⭐
56
FPGA-based high performance MPEG2 encoder for video compression. 基于 FPGA 的高性能 MPEG2 视频编码器,可实现视频压缩。
Parallella Riscv
⭐
55
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
Fpga Sata Hba
⭐
54
A SATA host (HBA) core based on Xilinx FPGA with GTH. Easy to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。
Fpga Sdcard Reader Spi
⭐
52
An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线),可以从FAT16或FAT32格式的SD卡中读取文件。
Corsair
⭐
52
Control and Status Register map generator for HDL projects
Enso
⭐
50
Ensō is a high-performance streaming interface for NIC-application communication.
Peakrdl
⭐
48
Control and status register code generator toolchain
Bigpulp
⭐
48
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
Aps Reborn
⭐
45
Методические материалы по разработке процессора архитектуры RISC-V
Misterynano
⭐
44
Atari STE MiSTery core for the Tang Nano 20k FPGA
Verilog Sha Family
⭐
43
Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。
Zynq Sandbox
⭐
41
a playground for xilinx zynq fpga experiments
Verilog Systemverilog Guide
⭐
41
Verilog/SystemVerilog Guide
Deep Neural Network Hardware Accelerator
⭐
40
SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software
Kronos
⭐
39
Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
Axi Crossbar
⭐
38
An AXI4 crossbar implementation in SystemVerilog
Fpu
⭐
37
IEEE 754 floating point library in system-verilog and vhdl
Peakrdl Regblock
⭐
36
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Brianhg Ddr3 Controller
⭐
34
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Systemverilogsha256
⭐
34
SHA256 in (System-) Verilog / Open Source FPGA Miner
Fpga_fast_serial_sort
⭐
30
a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
Gateware
⭐
30
A collection of little open source FPGA hobby projects
Nes_ecp5
⭐
29
NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board
Deepsocflow
⭐
28
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
Vdf Fpga
⭐
28
Implementation of an RSA VDF evaluator targeting FPGAs.
Sdram Controller
⭐
27
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
Openfpga Tutorials
⭐
26
A collection of tutorials and resources for the openFPGA platform.
Fpga Virtual Console
⭐
26
VT220-compatible console on Cyclone IV EP4CE55F23I7
Hdlconvertorast
⭐
25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
Fm_radio
⭐
24
Simple mono FM Radio.
Tech_cells_generic
⭐
24
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
Fpga Game Design
⭐
23
Fireboy & Water Girl in the Forest Temple implemented on an FPGA board for UIUC's ECE385 Digital Systems Laboratory.
My Verilog Examples
⭐
22
A place to keep my synthesizable verilog examples.
Ndk App Minimal
⭐
20
Minimal Application based on Network Development Kit (NDK) for FPGA cards
Hwthls
⭐
20
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
Intel Training Modules
⭐
20
Altera Pcie
⭐
19
Simple framework for building PCIe-based solutions for Altera FPGAs
Fpu Sp
⭐
19
IEEE 754 floating point library in system-verilog and vhdl
Verilog Fpga
⭐
19
Many peripherals in Verilog ready to use
Virtio
⭐
18
Virtio implementation in SystemVerilog
Fpga Ethernet Udp
⭐
17
An HDL design for sending data over Ethernet
Fpga_gameboy_watch
⭐
17
Full gameboy and gameboy color Verilog Implenentation
Usb
⭐
17
FPGA USB 1.1 Low-Speed Implementation
Fpga Cnn
⭐
16
This repo is for ECE44x (Fall2015-Spring2016)
Rfnoc Hls Atsc Rx
⭐
16
Fpga Hash Table
⭐
16
Simple hash table on Verilog (SystemVerilog)
Sha256hasher
⭐
15
SHA-256 IP core for ZedBoard (Zynq SoC)
10g Low Latency Ethernet
⭐
12
10G Low Latency Ethernet
C16_mister
⭐
12
Commodore C16 and Plus/4 for MiSTer
Verilog Sid Mos6581
⭐
12
MOS6581 SID chip emulator in SystemVerilog
Friscv
⭐
12
RISCV CPU implementation in SystemVerilog
Awesome Fpga List
⭐
12
A collection of some awesome public FPGA projects.
Fpga_spi
⭐
11
Connecting FPGA and Arduino using SPI.
Digital Hardware Modelling
⭐
11
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
Nanofox
⭐
11
A small RISC-V core (SystemVerilog)
Fpganes_release
⭐
11
Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog
Ics 2021spring Fdu
⭐
11
Introduction to Computer Systems (II), Spring 2021.
Svlogger
⭐
11
SystemVerilog Logger
Gpu
⭐
10
Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.
Resnet_fpga
⭐
10
UCSD CSE 237D Spring '20 Course Project
Verilog Basic
⭐
10
learn the combinational and sequential logic circuit.
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