Digital Hardware Modelling
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Vortex | 939 | 3 months ago | 51 | apache-2.0 | Verilog | |||||
| C5soc_opencl | 65 | 3 years ago | 8 | apache-2.0 | Verilog | |||||
| DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on. | ||||||||||
| Digital Hardware Modelling | 11 | 3 years ago | mit | VHDL | ||||||
| Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL) | ||||||||||
| Rc4 Verilog | 8 | 6 months ago | mit | C++ | ||||||
| EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher. | ||||||||||
| Cse Lab Solutions | 6 | 4 months ago | C | |||||||
| Comprehensive CSE Lab Solutions repo; encompassing all my lab manuals, codes, documents, and endsem questions from my B.Tech program (2020-2024). | ||||||||||
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