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Search results for verilog rtl

132 search results found

Chisel ⭐ 3,685

Chisel: A Modern Hardware Design Language

Verilator ⭐ 1,934

Verilator open-source SystemVerilog simulator and lint system

Darkriscv ⭐ 1,795

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Spinalhdl ⭐ 1,451

Scala based HDL

RTL, Cmodel, and testbench for NVDLA

Openlane ⭐ 1,148

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Openroad ⭐ 1,102

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Openwifi Hw ⭐ 560

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Riscv_vhdl ⭐ 552

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Various HDL (Verilog) IP Cores

Code generation tool for configuration and status registers

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Sv Tests ⭐ 257

Test suite designed to check compliance with the SystemVerilog standard.

Hardware implementation of the SHA-256 cryptographic hash function

Project Zipline ⭐ 251

Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

Fpga_readings ⭐ 249

Recipe for FPGA cooking

Verilog ⭐ 243

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Fpga Usb Device ⭐ 241

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个

Openroad Flow Scripts ⭐ 233

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/la

Piccolo ⭐ 227

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Veryl: A Modern Hardware Description Language

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Fpga Ftdi245fifo ⭐ 178

FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

Libsystemctlm Soc ⭐ 175

SystemC/TLM-2.0 Co-simulation framework

Open Register Design Tool ⭐ 169

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Autofpga ⭐ 153

A utility for Composing FPGA designs from Peripherals

Python-based hardware modeling framework

Fpga Sdcard Reader ⭐ 142

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

Fpga Jpeg Ls Encoder ⭐ 141

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

Tekno Kizil ⭐ 129

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

Vsdflow ⭐ 121

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Ope

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Fpga Can ⭐ 121

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

Simple 3-stage pipeline RISC-V processor

Oldland Cpu ⭐ 89

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

Haskell library for hardware description

A core language for rule-based hardware design 🦑

Fpga Ddr Sdram ⭐ 83

An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

Verilog Fixedpoint ⭐ 75

A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Fpga Sdfake ⭐ 69

Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。

Verilog Parser ⭐ 68

A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.

FPGA Based Apollo Guidance Computer

Hdl Tools ⭐ 60

Facilitates building open source tools for working with hardware description languages (HDLs)

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Cnn_open ⭐ 60

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Fpga Png Decoder ⭐ 57

An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图象解码器，可以从PNG文件中解码出原始像素。

Verilog Uart ⭐ 56

3 modules: UART receiver, UART transmitter, UART to AXI4 master. 3个模块：UART接收器、UART发送器、UART转AXI4交互式调试器

Fpga Sdcard Reader Spi ⭐ 52

An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。

Fpga Rmii Smii ⭐ 51

An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来连接LAN8720、KSZ8041TLI-S等

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

Fpga Lzma Compressor ⭐ 48

FPGA-based LZMA compressor. For generic lossless data compression. 基于FPGA的LZMA压缩器，用于通用数据压缩。

Original FPGA platform

Verilog Sha Family ⭐ 43

Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。

Sphinxcontrib Hdl Diagrams ⭐ 43

Sphinx Extension which generates various types of diagrams from Verilog code.

Python-based Portable IP-core Synthesis Framework for FPGA-based Computing

Hyperram ⭐ 39

Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC

Spinalcrypto ⭐ 36

SpinalHDL - Cryptography libraries

Pychip Py Hcl ⭐ 35

A Hardware Construct Language

hardware library for hwt (= ipcore repo)

Vga Clock ⭐ 33

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Higan Verilog ⭐ 33

This is a higan/Verilator co-simulation example/framework

Boxlambda ⭐ 30

FPGA based microcomputer sandbox for software and RTL experimentation

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

Hardposit Chisel3 ⭐ 26

Chisel library for Unum Type-III Posit Arithmetic

Crash_course_for_new_members ⭐ 26

Deep Learning & VLSI Crash Course for New Members

Hdlconvertorast ⭐ 25

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.

Design And Asic Implementation Of 32 Point Fft Processor ⭐ 20

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a

Ml4accel Dataset ⭐ 20

Dataset for ML-guided Accelerator Design

Gaussian noise generator Verilog IP core

Ethernet MAC 10/100 Mbps

QuSoC demo projects and template

Virtio implementation in SystemVerilog

Generic FIFO implementation with optional FWFT

This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).

Verilog Mini Demo ⭐ 17

Verilog极简教程

Sdaccel_chisel_integration ⭐ 16

Chisel Project for Integrating RTL code into SDAccel

Zbc The Zero Board Computer ⭐ 15

Based heavily on zet.aluzina.org and Terasic DE0

Face_detect_open ⭐ 15

A Voila-Jones face detector hardware implementation

Rdf 2019 ⭐ 14

Clarinet ⭐ 14

A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating custom functional units like posit arithmetic units.

Chisel Things for OFDM

Neuralhdl ⭐ 13

Open_regmodel ⭐ 13

🐥Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

Spinaldev ⭐ 12

Docker Development Environment for SpinalHDL

Openzcore ⭐ 12

powerpc processor prototype and an example of semiconductor startup biz plan

Vp2motion ⭐ 12

FPGA based motion controller for RepRap style 3D printers

MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).

Awesome Fpga List ⭐ 12

A collection of some awesome public FPGA projects.

Digital Hardware Modelling ⭐ 11

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

RISC-V BSV Specification

Open Source Network On Chip Router Rtl ⭐ 10

Lenet_rtl ⭐ 10

An LeNet RTL implement onto FPGA

Dsp Rtl Lib ⭐ 10

RTL Verilog library for various DSP modules

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