Piccolo
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Chisel | 3,685 | 9 | 13 days ago | 59 | April 14, 2023 | 397 | apache-2.0 | Scala | ||
| Chisel: A Modern Hardware Design Language | ||||||||||
| Verilator | 1,934 | 1 | 3 months ago | 8 | October 04, 2022 | 304 | lgpl-3.0 | C++ | ||
| Verilator open-source SystemVerilog simulator and lint system | ||||||||||
| Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
| Spinalhdl | 1,451 | 4 | 3 months ago | 140 | November 01, 2023 | 106 | other | Scala | ||
| Scala based HDL | ||||||||||
| Hw | 1,254 | 2 years ago | 193 | other | Verilog | |||||
| RTL, Cmodel, and testbench for NVDLA | ||||||||||
| Openlane | 1,148 | a month ago | 138 | apache-2.0 | Python | |||||
| OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. | ||||||||||
| Openroad | 1,102 | 3 months ago | 282 | bsd-3-clause | Verilog | |||||
| OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/ | ||||||||||
| Scr1 | 688 | 7 months ago | 3 | other | SystemVerilog | |||||
| SCR1 is a high-quality open-source RISC-V MCU core in Verilog | ||||||||||
| Openwifi Hw | 560 | 4 months ago | 5 | agpl-3.0 | Verilog | |||||
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware | ||||||||||
| Riscv_vhdl | 552 | 4 months ago | 2 | apache-2.0 | Verilog | |||||
| Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators | ||||||||||
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