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Search results for c plus plus verilog
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verilog
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76 search results found
Iverilog
⭐
2,521
Icarus Verilog
Verilator
⭐
1,934
Verilator open-source SystemVerilog simulator and lint system
Circt
⭐
1,431
Circuit IR Compilers and Tools
Silice
⭐
1,199
Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.
Openroad
⭐
1,102
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Xls
⭐
1,087
XLS: Accelerated HW Synthesis
Vtr Verilog To Routing
⭐
925
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Slang
⭐
505
SystemVerilog compiler and language services
Hal
⭐
490
HAL – The Hardware Analyzer
Beagle_sdr_gps
⭐
446
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
Opentimer
⭐
368
A High-performance Timing Analysis Tool for VLSI Systems
Hdlconvertor
⭐
258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
Degate
⭐
212
A modern and open-source cross-platform software for chips reverse engineering.
Dblclockfft
⭐
195
A configurable C++ generator of pipelined Verilog FFT cores
Hwt
⭐
189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Autofpga
⭐
153
A utility for Composing FPGA designs from Peripherals
Degate
⭐
151
Open source software for chip reverse engineering.
Metron
⭐
143
A C++ to Verilog translation tool with some basic guarantees that your code will work.
Verilogcreator
⭐
141
VerilogCreator is a QtCreator based IDE for Verilog 2005
Openfpgaduino
⭐
135
All open source file and project for OpenFPGAduino project
Logic
⭐
121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Tinygarble
⭐
113
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits
Istyle Verilog Formatter
⭐
112
Open source implementation of a Verilog formatter
Mdec
⭐
88
Attempt to verilog Implementation of Playstation 1 (PSX) chips.
Karuta
⭐
87
Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
Shang
⭐
85
The Shang high-level synthesis framework
Cordic
⭐
68
A series of CORDIC related projects
Systemctlm Cosim Demo
⭐
66
Systemc Clang
⭐
59
This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
Kratos
⭐
57
⚔️ Debuggable hardware generator
Fan_atpg
⭐
51
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
Avr
⭐
47
Reads a state transition system and performs property checking
Epicsim
⭐
43
EpicSim Project
Autopiper
⭐
40
Ctoverilog
⭐
37
A C to verilog compiler
Naja
⭐
34
Structural Netlist API (and more) for EDA post synthesis flow development
Higan Verilog
⭐
33
This is a higan/Verilator co-simulation example/framework
Iroha
⭐
30
Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
Gr Verilog
⭐
29
This is an OOT module for GNU Radio integrating verilog simulation feature
Ophidian
⭐
29
Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
Verilog Vcd Parser
⭐
28
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
Parser Verilog
⭐
24
A Standalone Structural Verilog Parser
Verilator
⭐
22
Fork of Verilator with prebuilt Ubuntu binaries (https://www.veripool.org/wiki/verilator)
Riscv
⭐
21
Open source ISS and logic RISC-V 32 bit project
Verilogast Cpp
⭐
20
C++17 implementation of an AST for Verilog code generation
Netlist Paths
⭐
19
A library and command-line tool for querying a Verilog netlist.
Naja Verilog
⭐
18
A standalone structural (gate-level) verilog parser
Grom8
⭐
16
GROM-8 CPU
Asynchronous Verilog Synthesiser
⭐
14
Synthesiser for Asynchronous Verilog Language
Riscv Atom
⭐
14
An open-source 32-bit RISC-V soft-core processor for FPGAs.
V2tt
⭐
14
This is the repository for the transpiler to compile Verilog to C++ code with TFHE library.
Iir Bandstop Filter
⭐
12
Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic
Qtcverilog
⭐
11
This is a stand-alone Verilog IDE derived from a QtCreator 3.6.1 subset featuring the VerilogCreator plugin
Coding_practice
⭐
11
This is the code I write for school, and some little code which is fun. Just recording what I learned.
Cosa2
⭐
11
Next generation cosa.
Systemc Tutorial
⭐
11
Brief SystemC getting started tutorial
Verilator Project Template
⭐
10
Template Verilator project for beginners
Nldb
⭐
10
Verilog netlist parser/database (derived from http://nldb.sourceforge.net)
Discretize
⭐
10
A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad
C Ll Verilog
⭐
10
An LLVM based mini-C to Verilog High-level Synthesis tool
32 Point Fft Verilog Design Based Dit Butterfly Algorithm
⭐
10
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
Mips Simulator
⭐
9
💻 A 5-stage pipeline MIPS CPU design in Haskell.
Hls_ldpc_dec
⭐
9
Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
Fwmpy
⭐
9
A multiply core generator
Jtag_dpi
⭐
9
JTAG DPI module for OpenRISC simulation with Verilator
Tsinghua Ee Miscellanea
⭐
8
🐾 Miscellanious projects during 2014-2018 in Dept. of Electronic Engineering, Tsinghua University
Yosys Bluespec
⭐
8
Yosys plugin for synthesis of Bluespec code
Pymtl Tut Hls
⭐
8
Tutorial for integrating PyMTL and Vivado HLS
Memepu
⭐
8
Rc4 Verilog
⭐
8
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
Riscv
⭐
8
32-bit soft RISCV processor for FPGA applications
Smtdv
⭐
8
make your verilog DUT test more smart
Phi
⭐
7
Hardware description language that tries not to suck
Gtuedu
⭐
7
Gebze Technical University
Vpreproc
⭐
7
A Preprocessor for Verilog HDL written in C++
Core_sdram_axi4
⭐
7
SDRAM controller with AXI4 interface
Libcircuit
⭐
6
libCircuit is a C++ Library for EDA software development
Ncore
⭐
6
A RISCV processor in system verilog
Iodine
⭐
6
Iodine: Verifying Constant-Time Execution of Hardware
Verilog
⭐
5
This is the Verilog 2005 parser used by VerilogCreator
Verilator
⭐
5
Gvi
⭐
5
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
Schematic_gui
⭐
5
Lightweight tool for schematic capture for digital designs
Jt5205
⭐
5
Verilog ADPCM decoder compatible with OKI MSM5205
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