Project Name	Stars	Most Recent Commit	Open Issues	License	Language
Vexriscv	2,135	4 months ago	100	mit	Assembly
A FPGA friendly 32 bit RISC-V CPU implementation
Vdt Plugin	15	6 years ago		gpl-3.0	Java
mirror of https://git.elphel.com/Elphel/vdt-plugin
Qtcverilog	11	2 years ago	1	gpl-3.0	C++
This is a stand-alone Verilog IDE derived from a QtCreator 3.6.1 subset featuring the VerilogCreator plugin
Yosys Bluespec	8	3 years ago		isc	C++
Yosys plugin for synthesis of Bluespec code
Verilog_emacsauto.vim	6	5 years ago	1		VimL
verilog filetype plugin to enable emacs verilog-mode autos
Rggen Verilog	5	4 months ago		mit	Ruby
Verilog writer plugin for RgGen
Hdl_plugin	5	13 years ago			VimL
Generate vhdl/verilog testbench file for vhdl files.

Alternatives To Qtcverilog

Select To Compare

Vexriscv ⭐ 2,135

A FPGA friendly 32 bit RISC-V CPU implementation

most recent commit 4 months ago

Vdt Plugin ⭐ 15

mirror of https://git.elphel.com/Elphel/vdt-plugin

most recent commit 6 years ago

Qtcverilog ⭐ 11

This is a stand-alone Verilog IDE derived from a QtCreator 3.6.1 subset featuring the VerilogCreator plugin

most recent commit 2 years ago

Yosys Bluespec ⭐ 8

Yosys plugin for synthesis of Bluespec code

most recent commit 3 years ago

Verilog_emacsauto.vim ⭐ 6

verilog filetype plugin to enable emacs verilog-mode autos

most recent commit 5 years ago

Rggen Verilog ⭐ 5

Verilog writer plugin for RgGen

most recent commit 4 months ago

Hdl_plugin ⭐ 5

Generate vhdl/verilog testbench file for vhdl files.

most recent commit 13 years ago

Suggest An Alternative To QtcVerilog

Alternative Project Comparisons

Qtcverilog vs Vexriscv

Qtcverilog vs Vdt Plugin

Qtcverilog vs Yosys Bluespec

Qtcverilog vs Verilog_emacsauto.vim

Qtcverilog vs Rggen Verilog

Qtcverilog vs Hdl_plugin

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