Dblclockfft
A configurable C++ generator of pipelined Verilog FFT cores
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Dblclockfft | 195 | 3 months ago | 3 | C++ | ||||||
| A configurable C++ generator of pipelined Verilog FFT cores | ||||||||||
| Fpga Application Development And Simulation | 96 | 9 months ago | 1 | mit | SystemVerilog | |||||
| 《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS). | ||||||||||
| Fft Dit Fpga | 94 | 12 years ago | 1 | mit | Verilog | |||||
| Verilog module for calculation of FFT. | ||||||||||
| Intfftk | 56 | a year ago | gpl-3.0 | VHDL | ||||||
| Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0. | ||||||||||
| Fftdemo | 34 | 3 months ago | Verilog | |||||||
| A demonstration showing how several components can be compsed to build a simulated spectrogram | ||||||||||
| Fpga Sdft | 32 | 4 years ago | 1 | Verilog | ||||||
| sliding DFT for FPGA, targetting Lattice ICE40 1k | ||||||||||
| Fp23fftk | 31 | 2 years ago | gpl-3.0 | VHDL | ||||||
| Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL). | ||||||||||
| Design And Asic Implementation Of 32 Point Fft Processor | 20 | 5 months ago | mit | Verilog | ||||||
| I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage. | ||||||||||
| Math | 15 | 4 years ago | n,ull | gpl-3.0 | MATLAB | |||||
| Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.) | ||||||||||
| Fftvisualizer | 13 | 6 years ago | Verilog | |||||||
| This project demonstrates DSP capabilities of Terasic DE2-115 | ||||||||||
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