Pymtl Tut Hls
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Openwifi | 3,363 | 5 months ago | 51 | agpl-3.0 | C | |||||
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software | ||||||||||
| Basic_verilog | 1,333 | 5 months ago | Verilog | |||||||
| Must-have verilog systemverilog modules | ||||||||||
| Xls | 1,087 | 3 months ago | 607 | apache-2.0 | C++ | |||||
| XLS: Accelerated HW Synthesis | ||||||||||
| Awesome Hdl | 830 | 4 months ago | 1 | |||||||
| Hardware Description Languages | ||||||||||
| Openwifi Hw | 560 | 5 months ago | 5 | agpl-3.0 | Verilog | |||||
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware | ||||||||||
| Fpga_readings | 249 | 3 years ago | 3 | apache-2.0 | Verilog | |||||
| Recipe for FPGA cooking | ||||||||||
| Hwt | 189 |  | 2 | 3 | 5 months ago | 34 | July 01, 2021 | 7 | mit | Python |
| VHDL/Verilog/SystemC code generator, simulator API written in python/c++ | ||||||||||
| Karuta | 87 | 2 years ago | 6 | gpl-3.0 | C++ | |||||
| Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development. | ||||||||||
| Skrskr | 76 | 2 years ago | 4 | other | Tcl | |||||
| The second place winner for DAC-SDC 2020 | ||||||||||
| Skynet | 75 | 4 years ago | 9 | other | Python | |||||
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