Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
Silice | 1,199 | 3 months ago | 73 | other | C++ | |||||
Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures. | ||||||||||
Hdmi | 892 | 8 months ago | 8 | other | SystemVerilog | |||||
Send video/audio over HDMI on an FPGA | ||||||||||
Pipelinec | 519 | 3 months ago | 82 | gpl-3.0 | Python | |||||
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. | ||||||||||
Limesdr Usb | 272 | 3 years ago | 4 | ANTLR | ||||||
USB 3.0 version of the LimeSDR board | ||||||||||
Openofdm | 251 | a year ago | 8 | apache-2.0 | Verilog | |||||
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder. | ||||||||||
Opl3_fpga | 225 | 4 years ago | 6 | lgpl-3.0 | VHDL | |||||
Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer | ||||||||||
Dblclockfft | 195 | 3 months ago | 3 | C++ | ||||||
A configurable C++ generator of pipelined Verilog FFT cores | ||||||||||
Autofpga | 153 | 3 months ago | 2 | gpl-3.0 | C++ | |||||
A utility for Composing FPGA designs from Peripherals | ||||||||||
Usbcorev | 146 | a year ago | 2 | other | Verilog | |||||
A full-speed device-side USB peripheral core written in Verilog. |