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Search results for verilog systemverilog
systemverilog
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verilog
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130 search results found
Verilator
⭐
1,934
Verilator open-source SystemVerilog simulator and lint system
Clash Compiler
⭐
1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
Scr1
⭐
688
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Minecrafthdl
⭐
595
A Verilog synthesis flow for Minecraft redstone circuits
Edalize
⭐
573
An abstraction library for interfacing EDA tools
Slang
⭐
505
SystemVerilog compiler and language services
Projf Explore
⭐
478
Project F brings FPGAs to life with exciting open-source designs you can build on.
Vscode Teroshdl
⭐
457
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Sv2v
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429
SystemVerilog to Verilog conversion
Svls
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376
SystemVerilog language server
Sv Parser
⭐
348
SystemVerilog parser library fully compliant with IEEE 1800-2017
Pymtl3
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344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
Surelog
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325
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Verigpu
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323
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Fpga Foc
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319
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器,用于驱动BLDC/PMSM电机。
Vscode Verilog Hdl Support
⭐
266
HDL support for VS Code
Ustc Rvsoc
⭐
261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。
Rggen
⭐
261
Code generation tool for configuration and status registers
Hdlconvertor
⭐
258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
Sv Tests
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257
Test suite designed to check compliance with the SystemVerilog standard.
Svlint
⭐
254
SystemVerilog linter
Verilog Mode
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231
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
Veryl
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225
Veryl: A Modern Hardware Description Language
Hwt
⭐
189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Fpga Ftdi245fifo
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178
FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。
Open Register Design Tool
⭐
169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Fpga Sdcard Reader
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142
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。
Fpga Jpeg Ls Encoder
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141
An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器,可实现高压缩率的无损/近无损图像压缩。
Eurorack Pmod
⭐
137
Hardware and gateware for getting started in FPGA-based audio synthesis with open source tools.
Hdl_checker
⭐
136
Repurposing existing HDL tools to help writing better code
Logic
⭐
121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Fpga Can
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121
An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
Fpga Application Development And Simulation
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96
《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
Veridian
⭐
88
A SystemVerilog Language Server
Verilog Fixedpoint
⭐
75
A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库,提供算术运算、与浮点数的互相转换,包含单周期和流水线两种实现。
Fpga Nfc
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73
Build an NFC (RFID) card reader using FPGA and simple circuit instead of RFID-specfic chip. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器,不需要专门的RFID芯片。
Fpga Sdfake
⭐
69
Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。
Open Nic Shell
⭐
67
AMD OpenNIC Shell includes the HDL source files
Uh Jls
⭐
61
FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器,用来进行无损图像压缩。
Svut
⭐
59
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Fpga Png Decoder
⭐
57
An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图象解码器,可以从PNG文件中解码出原始像素。
Fpga Mpeg2 Encoder
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56
FPGA-based high performance MPEG2 encoder for video compression. 基于 FPGA 的高性能 MPEG2 视频编码器,可实现视频压缩。
Riscv Simple Sv
⭐
56
A simple RISC V core for teaching
Ipxact2systemverilog
⭐
55
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
Fpga Sata Hba
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54
A SATA host (HBA) core based on Xilinx FPGA with GTH. Easy to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。
Vim Hdl
⭐
53
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
Fpga Sdcard Reader Spi
⭐
52
An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线),可以从FAT16或FAT32格式的SD卡中读取文件。
Corsair
⭐
52
Control and Status Register map generator for HDL projects
Autosva
⭐
50
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
Verilog Projects
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49
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
Peakrdl
⭐
48
Control and status register code generator toolchain
Verilog Sha Family
⭐
43
Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。
Ddlm
⭐
42
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
Verilog Systemverilog Guide
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41
Verilog/SystemVerilog Guide
Async_fifo
⭐
41
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
Axi Crossbar
⭐
38
An AXI4 crossbar implementation in SystemVerilog
Fpu
⭐
37
IEEE 754 floating point library in system-verilog and vhdl
Cosa
⭐
35
CoreIR Symbolic Analyzer
Brianhg Ddr3 Controller
⭐
34
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Systemverilogsha256
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34
SHA256 in (System-) Verilog / Open Source FPGA Miner
Ahb To Apb Bridge Verification
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34
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
Shunt
⭐
29
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
Deepsocflow
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28
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
Verilog Vcd Parser
⭐
28
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
Sdram Controller
⭐
27
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
Openfpga Tutorials
⭐
26
A collection of tutorials and resources for the openFPGA platform.
Crash_course_for_new_members
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26
Deep Learning & VLSI Crash Course for New Members
Hdlconvertorast
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25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
Fpga Game Design
⭐
23
Fireboy & Water Girl in the Forest Temple implemented on an FPGA board for UIUC's ECE385 Digital Systems Laboratory.
Formal_hw_verification
⭐
23
Trying to verify Verilog/VHDL designs with formal methods and tools
My Verilog Examples
⭐
22
A place to keep my synthesizable verilog examples.
Hwthls
⭐
20
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
Netlist Paths
⭐
19
A library and command-line tool for querying a Verilog netlist.
Verilog Fpga
⭐
19
Many peripherals in Verilog ready to use
Fpu Sp
⭐
19
IEEE 754 floating point library in system-verilog and vhdl
Vscode Systemverilog Support
⭐
18
[deprecated]use mshr-h/vscode-verilog-hdl-support
Svinst
⭐
18
Determines the modules declared and instantiated in a SystemVerilog file
Virtio
⭐
18
Virtio implementation in SystemVerilog
Usb
⭐
17
FPGA USB 1.1 Low-Speed Implementation
Fpga_gameboy_watch
⭐
17
Full gameboy and gameboy color Verilog Implenentation
Rggen
⭐
17
This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
Ivl_uvm
⭐
17
Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.
Dragonphy2
⭐
17
Open Source PHY v2
Fpga Hash Table
⭐
16
Simple hash table on Verilog (SystemVerilog)
Sha256hasher
⭐
15
SHA-256 IP core for ZedBoard (Zynq SoC)
Rggen Sample Testbench
⭐
14
Awesome Fpga List
⭐
12
A collection of some awesome public FPGA projects.
Int_fp_mac
⭐
12
INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
Fstdumper
⭐
12
Verilog VPI module to dump FST (Fast Signal Trace) databases
Friscv
⭐
12
RISCV CPU implementation in SystemVerilog
Verilog Sid Mos6581
⭐
12
MOS6581 SID chip emulator in SystemVerilog
Digital Hardware Modelling
⭐
11
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
Nirah
⭐
11
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
Svreal
⭐
11
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
Fpganes_release
⭐
11
Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog
Orbit
⭐
11
An HDL package manager.
Fpga_spi
⭐
11
Connecting FPGA and Arduino using SPI.
Svlogger
⭐
11
SystemVerilog Logger
Sequent
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10
Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog
Croyde Riscv
⭐
10
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
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