Verilog Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Openofdm | 251 | a year ago | 8 | apache-2.0 | Verilog | |||||
| Sythesizable, modular Verilog implementation of 802.11 OFDM decoder. | ||||||||||
| Bch_verilog | 57 | 2 years ago | 4 | other | Verilog | |||||
| Verilog based BCH encoder/decoder | ||||||||||
| Fpga Png Decoder | 57 | 7 months ago | gpl-3.0 | Verilog | ||||||
| An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图象解码器，可以从PNG文件中解码出原始像素。 | ||||||||||
| Verilog Projects | 49 | 5 years ago | n,ull | mit | Verilog | |||||
| This repository contains source code for past labs and projects involving FPGA and Verilog based designs | ||||||||||
| Core_jpeg | 31 | 4 years ago | apache-2.0 | Verilog | ||||||
| High throughput JPEG decoder in Verilog for FPGA | ||||||||||
| Design And Verification Of Ldpc Decoder | 17 | 7 years ago | Verilog | |||||||
| - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab. | ||||||||||
| Irig Decoder | 13 | a year ago | mit | Verilog | ||||||
| Firmware IRIG-B decoder | ||||||||||
| Hls_ldpc_dec | 9 | 5 years ago | gpl-3.0 | C++ | ||||||
| Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes).. | ||||||||||
| Fpga Video Decoder | 8 | 6 years ago | mit | Verilog | ||||||
| :space_invader: Design and implementation of a video decoder on an Altera Cyclone V FPGA board. | ||||||||||
| Viterbi Decoder In Verilog | 6 | 6 years ago | Verilog | |||||||
| An efficient implementation of the Viterbi decoding algorithm in Verilog | ||||||||||
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