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xilinx-vivado x

10 search results found

Wb2axip ⭐ 409

Bus bridges and other odds and ends

Hdl_checker ⭐ 136

Repurposing existing HDL tools to help writing better code

Verilog Projects ⭐ 49

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

100daysofrtl ⭐ 12

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

Rules_vivado ⭐ 11

Bazel rules for Xilinx Vivado

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Computer Systems Ucas ⭐ 8

中国科学院大学计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session

Verilog_calculator_matrix_multiplication ⭐ 8

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

Rc4 Verilog ⭐ 8

EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.

Barebonescortexm0 ⭐ 7

Extremely basic CortexM0 SoC based on ARM DesignStart Eval

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