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Search results for verilog risc v

66 search results found

Vexriscv ⭐ 2,135

A FPGA friendly 32 bit RISC-V CPU implementation

Darkriscv ⭐ 1,795

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

E200_opensource ⭐ 1,688

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Neorv32 ⭐ 1,337

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

SERV - The SErial RISC-V CPU

E203_hbirdv2 ⭐ 741

The Ultra-Low Power RISC-V Core

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Riscv_vhdl ⭐ 552

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Kianriscv ⭐ 396

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .

Risc V Single Cycle Cpu ⭐ 380

A RISC-V 32bit single-cycle CPU written in Logisim

RISC-V CPU Core (RV32IM)

Verigpu ⭐ 323

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Biriscv ⭐ 300

32-bit Superscalar RISC-V CPU

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Ridecore ⭐ 185

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Riscv Bitmanip ⭐ 174

Working draft of the proposed RISC-V Bitmanipulation extension

Fomu Workshop ⭐ 148

Support files for participating in a Fomu workshop

Tekno Kizil ⭐ 129

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

Ice40_ultraplus_examples ⭐ 115

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

Simple 3-stage pipeline RISC-V processor

Icestation 32 ⭐ 107

Compact FPGA game console

Tang_e203_mini ⭐ 103

LicheeTang 蜂鸟E203 Core

Fedar F1 Rv64im ⭐ 84

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

XCrypto: a cryptographic ISE for RISC-V

Fpga Rocket Chip ⭐ 79

Wrapper for Rocket-Chip on FPGAs

Yet Another RISC-V Implementation

Awesome Dv ⭐ 76

Awesome ASIC design verification

3-stage RV32IMACZb* processor with debug

Tree Core Ide ⭐ 56

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Riscv Simple Sv ⭐ 56

A simple RISC V core for teaching

Riscy Soc ⭐ 54

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

Featherweight RISC-V implementation

Engine V ⭐ 49

SoftCPU/SoC engine-V

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Airisc_core_complex ⭐ 48

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals for embedded AI applications and smart sensors.

Verilog implementation of a RISC-V core

Dual-issue RV64IM processor for fun & learning

Getting Started ⭐ 46

List of ideas for getting started with TimVideos projects

Neorv32 Setups ⭐ 44

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Converts ELF files to HEX files that are suitable for Verilog's readmemh.

Eveide_light ⭐ 41

A lightweight IDE that supports verilog simulation and RISC-V code compilation

Super Miyamoto Sprint ⭐ 41

Homebrew game for homebrew FPGA game console

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Fpga101 Workshop ⭐ 38

FPGA 101 - Workshop materials

Axi Crossbar ⭐ 38

An AXI4 crossbar implementation in SystemVerilog

IEEE 754 floating point library in system-verilog and vhdl

A small SoC with a pipeline 32-bit RISC-V CPU.

phoeniX RISC-V Processor

Riscv_cpu ⭐ 30

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

Clash Riscv ⭐ 30

A RiscV processor implementing the RV32I instruction set written in Clash

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Hyperbus ⭐ 29

A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

Gateware ⭐ 26

IP submodules, formatted for easier CI integration

Computer Architecture Task 2 ⭐ 25

Riscv32 CPU Project

Riscv Soc Cores ⭐ 23

KISCV, a KISS principle riscv32i CPU

Open source ISS and logic RISC-V 32 bit project

Riftcore ⭐ 20

RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System

IEEE 754 floating point library in system-verilog and vhdl

Proj7 Terminus ⭐ 19

可运行OS的RISCV-64的硬件模拟器设计与实现

Picorv32_xilinx ⭐ 19

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

QuSoC demo projects and template

Scarv Cpu ⭐ 18

SCARV: a side-channel hardened RISC-V platform

Riscv Atom ⭐ 14

An open-source 32-bit RISC-V soft-core processor for FPGAs.

RISCV CPU implementation in SystemVerilog

Awesome Fpga List ⭐ 12

A collection of some awesome public FPGA projects.

Toast Rv32i ⭐ 11

A Pipelined RISC-V RV32I Core in Verilog

Riscv Core ⭐ 11

A customized RISCV core made using verilog

RISC-V BSV Specification

Riscv Cpu ⭐ 11

SJTU Computer Architecture(1) Hw

Zc Riscv Core ⭐ 11

in-line FPGA-CPU协同分组处理

M-extension for RISC-V cores.

Riscv_soc ⭐ 10

Basic RISC-V Test SoC

Croyde Riscv ⭐ 10

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

Riscv Core ⭐ 9

5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany

Vsdbabysoc ⭐ 9

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

Little Cpu ⭐ 8

Little cpu in verilog.

Riscv32_lcc ⭐ 8

32-bit soft RISCV processor for FPGA applications

Computer Architecture ⭐ 8

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003 , Introduction to Computer Organisation in IIT Madras.

Riscv_verilog ⭐ 8

RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.

De10 Nano Riscv ⭐ 7

A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano

科学狂人Carl的RISC-V核心 | Mad Scientist Carl's Core (RISC-V)

LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.

RISC-V SingleCycle/Pipeline CPU (lab of ZJU Computer System Series)

Fpga_riscv_cpu ⭐ 6

fpga verilog risc-v rv32i cpu

Craft2 Chip ⭐ 6

Craft 2 top-level repository

Cpu Riscv ⭐ 6

ACM Class 2017 Computer Architecture

Risc V Cpu ⭐ 6

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

A RISCV processor in system verilog

Wb_riscvscale ⭐ 6

This is a wishbone compliant RISCV Vscale core intended to run part of FuseSoC project with other (open)cores.

Accomdemy_rv32i ⭐ 5

伴伴學 RISC-V RV32I Architecture CPU

Armleocpu ⭐ 5

Multicore RISC-V CPU RV64GC w/ MMU, Cache. Capable of booting Linux. Work in progress to execute first instruction

Ecp5_brieysoc ⭐ 5

Briey SoC on ECP5 (ICESugar Pro)

F Of E Tools ⭐ 5

Repository for the tools for the Foundations of Embedded Systems online course (https://f-of-e.org).

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