Neorv32 Setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Aib Phy Hardware | 57 | a year ago | 1 | apache-2.0 | Verilog | |||||
| Neorv32 Setups | 44 | 3 months ago | 5 | bsd-3-clause | VHDL | |||||
| 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains. | ||||||||||
| Brianhg Ddr3 Controller | 34 | 2 years ago | SystemVerilog | |||||||
| DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included. | ||||||||||
| Thunderclap Fpga Arria10 | 21 | 5 years ago | Verilog | |||||||
| Thunderclap hardware for Intel Arria 10 FPGA | ||||||||||
| Hps2fpgamapping | 21 | 3 years ago | 1 | mit | Verilog | |||||
| SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V) | ||||||||||
| Centaur | 14 | 7 years ago | apache-2.0 | Verilog | ||||||
| Centaur, a framework for hybrid CPU-FPGA databases | ||||||||||
| Jtag_interface | 14 | 4 months ago | 1 | mit | C | |||||
| A template for establishing a JTAG connection between the MCU and FPGA chip on the Arduino MKR Vidor 4000 | ||||||||||
| Sp I586 | 8 | 7 years ago | Verilog | |||||||
| soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk contained in the SPI flash. | ||||||||||
| Mastering Fpgasic Book | 8 | 2 years ago | ||||||||
| :book: Mastering FPGASIC Book | ||||||||||
| Reconfig | 7 | 5 months ago | mit | HTML | ||||||
| Implementation of various projects on Cyclone V FPGA | ||||||||||
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