Riftcore
RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Fpga Imaging Library | 271 | 9 years ago | lgpl-2.1 | Verilog | ||||||
| An open source library for image processing on FPGA. | ||||||||||
| Breaks | 138 | 6 months ago | 2 | cc0-1.0 | Verilog | |||||
| Nintendo Entertainment System (NES) / Famicom / Famiclones chip reversing | ||||||||||
| Chiphack | 43 | 6 years ago | 2 | other | Verilog | |||||
| Repository and Wiki for Chip Hack events. | ||||||||||
| Riftcore | 20 | 2 years ago | apache-2.0 | Verilog | ||||||
| RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System | ||||||||||
| Ethpipe | 14 | 9 years ago | 1 | Verilog | ||||||
| EtherPIPE: an Ethernet character device for packet processing | ||||||||||
| Onetswitch30 | 7 | 8 years ago | 2 | lgpl-2.1 | Verilog | |||||
| Reference Designs for ONetSwitch30 | ||||||||||
| Fky2015 | 5 | 4 months ago | ||||||||
| Code for Good. | ||||||||||
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