Fedar F1 Rv64im

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
Alternatives To Fedar F1 Rv64im
Project NameStarsDownloadsRepos Using ThisPackages Using ThisMost Recent CommitTotal ReleasesLatest ReleaseOpen IssuesLicenseLanguage
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A FPGA friendly 32 bit RISC-V CPU implementation
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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
E200_opensource1,688
3 years ago33apache-2.0Verilog
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Neorv321,337
2 months ago15bsd-3-clauseVHDL
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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SERV - The SErial RISC-V CPU
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E203_hbirdv2741
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The Ultra-Low Power RISC-V Core
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SCR1 is a high-quality open-source RISC-V MCU core in Verilog
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Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Kianriscv396
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KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .
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