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Reverse Engineering ⭐ 10,949

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Rt Thread ⭐ 9,221

RT-Thread is an open source IoT real-time operating system (RTOS).

Unicorn ⭐ 6,921

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

Xv6 Riscv ⭐ 5,550

Alios Things ⭐ 4,437

面向IoT领域的、高可伸缩的物联网操作系统，可去官网了解更多信息https://www.aliyun

A self-hosting and educational C optimizing compiler

NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching

Eclipse Plugins ⭐ 552

The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.

Edk2 Platforms ⭐ 486

EDK II sample platform branches and tags

Dirtyjtag ⭐ 452

JTAG probe firmware

Pulp Dronet ⭐ 428

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

Riscv Openocd ⭐ 395

Fork of OpenOCD that has RISC-V support

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Freedom U Sdk ⭐ 260

Freedom U Software Development Kit (FUSDK)

Mini Riscv Os ⭐ 242

Build a minimal multi-tasking OS kernel for RISC-V from scratch

Risc V Tlm ⭐ 207

RISC-V SystemC-TLM simulator

Mempool ⭐ 203

A 256-RISC-V-core system with low-latency access into shared L1 memory.

Zenroom ⭐ 185

Embedded no-code VM executing human-like language to manipulate data and process cryptographic operations.

Esp32_usb_soft_host ⭐ 165

ESP32 software USB host through general IO pins. We can connect up to 4 USB-LS HID (keyboard mouse joystick) devices simultaneously.

Xv6 Riscv Fall19 ⭐ 152

6.S081/6.828 lab repo for fall 2019

UART based embedded shell for embedded systems. Intended to be used for learning, experimenting and diagnostics.

Arv32 Opt ⭐ 141

[Tested successfully] Linux on Arduino UNO / atmega328p port of mini-rv32ima. Let's run Linux on the world's worst Linux PC (and beat Dmitry Grinberg)

Imperas Riscv Tests ⭐ 123

Riscy Business ⭐ 117

RISC-V Virtual Machine

Penglai Enclave Spmp ⭐ 116

Penglai Enclave is an open-sourced, secure and scalable TEE system for RISC-V.

Ft800 Ft813 ⭐ 115

Multi-Platform C code Library for EVE graphics controllers from FTDI / Bridgetek (FT810, FT811, FT812, FT813, BT815, BT816, BT817, BT818)

Icestation 32 ⭐ 107

Compact FPGA game console

Phoenix Rtos Kernel ⭐ 99

Phoenix-RTOS microkernel repository

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

Nuclei Sdk ⭐ 91

Nuclei RISC-V Software Development Kit

No PR will be accepted for now, but feel free to submit issue, very appreciated.

Risc V Linux ⭐ 84

This repository provides a Linux kernel bootable on RISC-V boards from SiFive

Riscv_em ⭐ 80

Simple risc-v emulator, able to run linux, written in C.

Fpga Rocket Chip ⭐ 79

Wrapper for Rocket-Chip on FPGAs

Quasisoc ⭐ 77

No-MMU Linux capable RISC-V SoC designed to be useful.

SL_SDK provides an easy-to-use software framework with united HAL and OSAL, also including a runtime environment to speed-up development for embedded devices like COTEX-M, RISC-V and so on.

Multizone Sdk ⭐ 74

MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn't define TrustZone-like primitives to provide hardware separation. To shield critical functionality from untrusted third-party components, MultiZone provides hardware-enforced, software-defined separation of multi

UNIX-like operating system written in C and C++

Simd_utils ⭐ 65

A header only library implementing common mathematical functions using SIMD intrinsics

Risc V Computer 2.0 ⭐ 64

An educational RISC-V based computer build with Logisim

Development Boards ⭐ 63

Collection of various development boards for microcontrollers (e.g. CH55x, CH32V003, PY32F002A, STM32) and CPLDs.

An optimized neural network operator library for chips base on Xuantie CPU.

Cyancore ⭐ 58

A unified software platform for embedded system projects ...

Nucleusrv ⭐ 56

NucleusRV - A 32-bit 5 staged pipelined risc-v core.

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

Nuclei Microcontroller Software Interface Standard Development Repo

FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Hydrausb3_fw ⭐ 48

HydraUSB3 (WCH CH569) open source test firmware / examples / libraries to experiment with streaming / high-speed protocols (USB2 HS, USB3 SS, HSPI, SerDes...)

Firechip ⭐ 46

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

Xv6 K210 ⭐ 45

Port XV6 to K210 board!

Standalone C compiler for RISC-V and ARM

Riscv Fw Infrastructure ⭐ 44

Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...

Fast constant-time AES implementations on 32-bit architectures

Rocket Rocc Examples ⭐ 43

Tests for example Rocket Custom Coprocessors

Openocd_cmsis Dap_v2 ⭐ 42

支持CMSIS-DAP v2接口协议，支持ARM、RISCV、ESP32等目标芯片，详见Wiki及release

Kendryte Openmv ⭐ 42

Super Miyamoto Sprint ⭐ 41

Homebrew game for homebrew FPGA game console

Riscv Coremark ⭐ 40

Setup scripts and files needed to compile CoreMark on RISC-V

C Ninja Listings ⭐ 38

Lower level assembly and C baremetal programming on RISC-V CPUs. Source code listings from the C-Ninja, in Pyjama! book.

Openpicortos ⭐ 36

Very small, safe, lightning fast, yet portable preemptive RTOS with SMP support

Qemu Pinning ⭐ 36

My QEMU fork with pinning (affinity) support and a few tweaks.

Frankenlibc ⭐ 35

Tools for running rump unikernels in userspace

Valgrind Riscv64 ⭐ 35

Valgrind with support for the RISCV64/Linux platform.

Silice Playground ⭐ 34

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

Yuanix Riscv Os ⭐ 34

Build a minimal kernel for RISC-V

Riscv64 Nommu Buildroot ⭐ 32

Riscv_cpu ⭐ 30

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

Tg Nexus Trace ⭐ 29

RISC-V Nexus Trace TG documentation and reference code

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining

Riscv Emulator ⭐ 23

A project for learning RISC-V architecture purpose

MDX — A BSD-style RTOS

Nuttx Star64 ⭐ 21

Apache NuttX RTOS for Pine64 Star64 64-bit RISC-V SBC (StarFive JH7110)

Multizone Iot Sdk ⭐ 19

MultiZone® Trusted Firmware is the quick and safe way to build secure IoT applications with any RISC-V processor. It provides secure access to commercial and private IoT clouds, real-time monitoring, secure boot, and remote firmware updates. The built-in Trusted Execution Environment provides hardware-enforced separation ...

Onefileforth ⭐ 18

A single file implementation of a non-standard Forth written in the FIG style

Hello C90 ⭐ 18

Hello world in C90 (ANSI C) built for Intel/AMD, PowerPC, System z, ARM, MIPS, RISC-V

TBM Bare metal tests

Some_tiny_interpreters ⭐ 17

some interpreters with high protability

ARINC653 Multi-Partition Operating System Based On RISC-V, capable of running on SiFive HiFive Unmatched.

Multizone Linux ⭐ 16

MultiZone® Security Enclave for Linux

Bbl Ucore ⭐ 16

uCore OS Labs on Berkeley bootloader

Minidecaf Tests ⭐ 16

The MiniDecaf test cases.

Corepartition ⭐ 16

Universal Cooperative Multithread Lib with real time Scheduler that was designed to work, virtually, into any modern micro controller or Microchip and, also, for user space applications for modern OS (Mac, Linux, Windows) or on FreeRTOS as well. Supports C and C++

Licheetang_openocd ⭐ 15

forked from https://github.com/riscv/riscv-openocd.git,and add falsh support for LicheeTang

9444 RISC-V 64IMA CPU and related tools and peripherals.

Kendryte K210 BSP for RT-Thread

Riscv Gd32vf103 Demo ⭐ 13

Simple demo firmware for the RISC-V GD32VF103

Esp Isa Sim ⭐ 13

Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project

InfoSec Binary Hex Editor with Retro Disassemblers

LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V

L1 R1：WCH RISC-V4A BLE SoC (CH583/CH582/CH581)

Rv32 Sail ⭐ 11

32-bit RISC-V Emulator

Toast Rv32i ⭐ 11

A Pipelined RISC-V RV32I Core in Verilog

Multizone Api ⭐ 11

MultiZone free and open API definition

A Unix-like and microkernel-based operating system for ARM

in-line FPGA-CPU协同分组处理

UNIXv7 ported to RISC-V, specifically the Longnan Nano SBC

Limine C Template Portable ⭐ 10

A simple template for building a portable, Limine-compliant kernel in C.

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