| openhwgroup/cva6 |
1,946 |
|
0 |
0 |
over 2 years ago |
0 |
|
157 |
other |
Assembly |
| The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux |
| olofk/serv |
1,158 |
|
0 |
0 |
over 2 years ago |
0 |
|
17 |
isc |
Verilog |
| SERV - The SErial RISC-V CPU |
| riscvarchive/riscv-cores-list |
747 |
|
0 |
0 |
about 5 years ago |
0 |
|
|
|
|
| RISC-V Cores, SoC platforms and SoCs |
| ultraembedded/riscv |
364 |
|
0 |
0 |
over 4 years ago |
0 |
|
4 |
bsd-3-clause |
Verilog |
| RISC-V CPU Core (RV32IM) |
| ultraembedded/biriscv |
300 |
|
0 |
0 |
over 4 years ago |
0 |
|
8 |
apache-2.0 |
Verilog |
| 32-bit Superscalar RISC-V CPU |
| pulp-platform/ara |
276 |
|
0 |
0 |
over 2 years ago |
0 |
|
57 |
other |
C |
| The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core |
| sld-columbia/esp |
267 |
|
0 |
0 |
over 2 years ago |
0 |
|
34 |
other |
C |
| Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy |
| pulp-platform/mempool |
203 |
|
0 |
0 |
over 2 years ago |
0 |
|
8 |
apache-2.0 |
C |
| A 256-RISC-V-core system with low-latency access into shared L1 memory. |
| KASIRGA-KIZIL/tekno-kizil |
129 |
|
0 |
0 |
almost 3 years ago |
0 |
|
3 |
gpl-3.0 |
Verilog |
| KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi |
| drom/awesome-riscv |
96 |
|
0 |
0 |
about 3 years ago |
0 |
|
1 |
|
|
| 😎 A curated list of awesome RISC-V implementations |
