Mempool
A 256-RISC-V-core system with low-latency access into shared L1 memory.
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Cva6 | 2,042 | a month ago | 157 | other | Assembly | |||||
| The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux | ||||||||||
| Serv | 1,158 | 4 months ago | 17 | isc | Verilog | |||||
| SERV - The SErial RISC-V CPU | ||||||||||
| Riscv Cores List | 791 | 3 years ago | n,ull | |||||||
| RISC-V Cores, SoC platforms and SoCs | ||||||||||
| Riscv | 364 | 3 years ago | 4 | bsd-3-clause | Verilog | |||||
| RISC-V CPU Core (RV32IM) | ||||||||||
| Biriscv | 300 | 3 years ago | 8 | apache-2.0 | Verilog | |||||
| 32-bit Superscalar RISC-V CPU | ||||||||||
| Ara | 276 | 5 months ago | 57 | other | C | |||||
| The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core | ||||||||||
| Esp | 267 | 4 months ago | 34 | other | C | |||||
| Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy | ||||||||||
| Mempool | 203 | 4 months ago | 8 | apache-2.0 | C | |||||
| A 256-RISC-V-core system with low-latency access into shared L1 memory. | ||||||||||
| Tekno Kizil | 129 | 9 months ago | 3 | gpl-3.0 | Verilog | |||||
| KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi | ||||||||||
| Awesome Riscv | 96 | a year ago | 1 | |||||||
| 😎 A curated list of awesome RISC-V implementations | ||||||||||
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