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The Top 23 Asic Open Source Projects

Open source projects categorized as Asic
Categories > Hardware > Asic
Grin ⭐ 5,026
Minimal implementation of the Mimblewimble protocol.
dependent packages 13total releases 28most recent commit 3 months agocargo grin_util} Downloads
Skywater Pdk ⭐ 2,627
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
total releases 1most recent commit 8 months ago
Cva6 ⭐ 2,042
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
most recent commit a month ago
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87most recent commit 3 months ago
Serv ⭐ 1,158
SERV - The SErial RISC-V CPU
most recent commit 4 months ago
Openlane ⭐ 1,148
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
most recent commit a month ago
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26most recent commit 3 months agopypi fusesoc} Downloads
Axi ⭐ 834
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
most recent commit 4 months ago
Riscv Cores List ⭐ 791
RISC-V Cores, SoC platforms and SoCs
most recent commit 3 years ago
Dss ⭐ 719
Digital Signature Service : creation, extension and validation of advanced electronic signatures
dependent packages 5total releases 6most recent commit 3 months ago
Vunit ⭐ 678
VUnit is a unit testing framework for VHDL/SystemVerilog
dependent packages 5total releases 87most recent commit 24 days agopypi vunit-hdl} Downloads
Btcgpu ⭐ 628
Current work on BTCGPU
most recent commit a year ago
Gemmini ⭐ 562
Berkeley's Spatial Array Generator
most recent commit 5 months ago
Embedded Neural Network ⭐ 547
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
most recent commit 3 months ago
Riscv ⭐ 364
RISC-V CPU Core (RV32IM)
most recent commit 3 years ago
Poc ⭐ 324
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
most recent commit 4 years ago
Cores ⭐ 302
Various HDL (Verilog) IP Cores
most recent commit 3 years ago
Biriscv ⭐ 300
32-bit Superscalar RISC-V CPU
most recent commit 3 years ago
Ara ⭐ 276
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
most recent commit 5 months ago
Gf180mcu Pdk ⭐ 270
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
total releases 1most recent commit a year ago
Esp ⭐ 267
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
most recent commit 4 months ago
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62most recent commit 3 months ago
Surf ⭐ 259
A huge VHDL library for FPGA development
most recent commit 5 months ago
The 10 Most Depended On Asic Open Source Projects
Systemrdl Compiler ⭐ 212
SystemRDL 2.0 language compiler front-end
dependent packages 14total releases 50latest release November 09, 2023most recent commit 3 months agopypi systemrdl-compiler} Downloads
Grin ⭐ 5,026
Minimal implementation of the Mimblewimble protocol.
dependent packages 13total releases 28latest release March 17, 2022most recent commit 3 months agocargo grin_util} Downloads
Vunit ⭐ 678
VUnit is a unit testing framework for VHDL/SystemVerilog
dependent packages 5total releases 87latest release April 23, 2023most recent commit 24 days agopypi vunit-hdl} Downloads
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26latest release November 17, 2023most recent commit 3 months agopypi fusesoc} Downloads
Dss ⭐ 719
Digital Signature Service : creation, extension and validation of advanced electronic signatures
dependent packages 5total releases 6latest release November 03, 2023most recent commit 3 months ago
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 6 months agopypi peakrdl} Downloads
Dfiant ⭐ 56
DFiant: A Dataflow Hardware Descripition Language
dependent packages 4total releases 3latest release September 05, 2023most recent commit 7 months ago
Node Xgminer ⭐ 8
A cgminer API client for node.js (supports all cgminer variants)
dependent packages 3total releases 7latest release March 21, 2014most recent commit 6 years agonpm xgminer} Downloads
Skillbridge ⭐ 140
A seamless python to Cadence Virtuoso Skill interface
dependent packages 3total releases 44latest release August 18, 2023most recent commit 5 months agopypi skillbridge} Downloads
Peakrdl Ipxact ⭐ 29
Import and export IP-XACT XML register models
dependent packages 2total releases 17latest release August 31, 2023most recent commit 6 months agopypi peakrdl-ipxact} Downloads
The 10 Latest Releases In Asic Open Source Projects
Pyasic ⭐ 61
A simplified and standardized interface for Bitcoin ASICs.
total releases 229latest release November 30, 2023most recent commit 3 months ago
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26latest release November 17, 2023most recent commit 3 months agopypi fusesoc} Downloads
Fiks Asice Dotnet ⭐ 8
Library for creating, reading and validating ASIC-E packages
dependent packages 1total releases 26latest release November 14, 2023most recent commit 5 months agonuget KS.Fiks.ASiC-E} Downloads
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87latest release November 11, 2023most recent commit 3 months ago
Systemrdl Compiler ⭐ 212
SystemRDL 2.0 language compiler front-end
dependent packages 14total releases 50latest release November 09, 2023most recent commit 3 months agopypi systemrdl-compiler} Downloads
Dss ⭐ 719
Digital Signature Service : creation, extension and validation of advanced electronic signatures
dependent packages 5total releases 6latest release November 03, 2023most recent commit 3 months ago
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 6 months agopypi peakrdl} Downloads
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62latest release October 18, 2023most recent commit 3 months ago
Peakrdl Regblock ⭐ 36
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
total releases 20latest release October 12, 2023most recent commit 4 months ago
Mflowgen ⭐ 169
mflowgen -- A Modular ASIC/FPGA Flow Generator
total releases 6latest release September 21, 2023most recent commit 3 months ago
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