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489 search results found

Opentitan ⭐ 2,108

OpenTitan: Open source silicon root of trust

Verilator ⭐ 1,934

Verilator open-source SystemVerilog simulator and lint system

Clash Compiler ⭐ 1,336

Haskell to VHDL/Verilog/SystemVerilog compiler

Verible ⭐ 1,179

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Send video/audio over HDMI on an FPGA

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

RSD: RISC-V Out-of-Order Superscalar Processor

Swerv_eh1 ⭐ 746

A directory of Western Digital’s RISC-V SweRV Cores

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Lets Prove Leftpad ⭐ 598

Proving leftpad correct in a dozen different ways

Minecrafthdl ⭐ 595

A Verilog synthesis flow for Minecraft redstone circuits

Edalize ⭐ 573

An abstraction library for interfacing EDA tools

Pcileech Fpga ⭐ 525

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

SystemVerilog compiler and language services

Black Parrot ⭐ 494

A Linux-capable RISC-V multicore for and by the world

Projf Explore ⭐ 478

Project F brings FPGAs to life with exciting open-source designs you can build on.

Vscode Teroshdl ⭐ 457

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Fpga Foc ⭐ 444

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

SystemVerilog to Verilog conversion

Basejump_stl ⭐ 421

BaseJump STL: A Standard Template Library for SystemVerilog

Common_cells ⭐ 384

Common SystemVerilog components

SystemVerilog language server

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

Nontrivial Mips ⭐ 362

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Core V Verif ⭐ 359

Functional verification project for the CORE-V family of RISC-V cores.

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Sv Parser ⭐ 348

SystemVerilog parser library fully compliant with IEEE 1800-2017

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Deepfloat ⭐ 333

An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.

Surelog ⭐ 325

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Verigpu ⭐ 323

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Tvip Axi ⭐ 276

Pulpissimo ⭐ 272

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

Vscode Verilog Hdl Support ⭐ 266

HDL support for VS Code

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Code generation tool for configuration and status registers

Hdlconvertor ⭐ 258

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

Sv Tests ⭐ 257

Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog linter

Verilog Mode ⭐ 231

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

Veryl: A Modern Hardware Description Language

80186 compatible SystemVerilog CPU core and FPGA reference design

Nitefury And Litefury ⭐ 212

Public repository for Litefury & Nitefury

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

Bsg_manycore ⭐ 208

Tile based architecture designed for computing efficiency, scalability and generality

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Cv32e40x ⭐ 184

4 stage, in-order, compute RISC-V core based on the CV32E40P

100daysofrtl ⭐ 181

100 Days of RTL

Fpga Ftdi245fifo ⭐ 178

FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

Open Register Design Tool ⭐ 169

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Openfpga Nes ⭐ 157

NES for the Analogue Pocket

Riscv Dbg ⭐ 153

RISC-V Debug Support for our PULP RISC-V Cores

Core V Mcu ⭐ 153

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Nes_mister ⭐ 147

Fpga Sdcard Reader ⭐ 142

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

Fpga Jpeg Ls Encoder ⭐ 141

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

Saturn_mister ⭐ 138

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

Hdl_checker ⭐ 136

Repurposing existing HDL tools to help writing better code

Starshipraider ⭐ 134

Open hardware test equipment

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Fpga Can ⭐ 121

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

Cv32e40s ⭐ 115

4 stage, in-order, secure RISC-V core based on the CV32E40P

Intel Fpga Bbb ⭐ 101

Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs

Fpga Application Development And Simulation ⭐ 96

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

Uvmreference ⭐ 93

Reference examples and short projects using UVM Methodology

Network on Chip Implementation written in SytemVerilog

Veridian ⭐ 88

A SystemVerilog Language Server

FX68K 68000 cycle accurate SystemVerilog core

Fpga Partial Reconfig ⭐ 84

Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

A simple superscalar out of order RISC-V (micro)processor

Cheshire ⭐ 80

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Pcileech Wifi ⭐ 79

pcileech-fpga with wireless card emulation

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

Verilog Fixedpoint ⭐ 75

A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Snestang ⭐ 73

Super Nintendo Entertainment System for Tang Primer 25K FPGA

Fpga Nfc ⭐ 73

Build an NFC (RFID) card reader using FPGA and simple circuit instead of RFID-specfic chip. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。

Uvm Tutorial For Candy Lovers ⭐ 73

Source code repo for UVM Tutorial for Candy Lovers

Ahb3lite_interconnect ⭐ 71

AHB3-Lite Interconnect

Analogue Pocket Utils ⭐ 71

Collection of IP and information on how to develop for openFPGA and Analogue Pocket

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

Superscalar Riscv Cpu ⭐ 69

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

Fpga Sdfake ⭐ 69

Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。

Tiny Synth ⭐ 69

Verilog code for a simple synth module; developed on TinyFPGA BX

Redip Sid ⭐ 69

MOS 6581 / 8580 SID FPGA emulation platform

Rohd Hcl ⭐ 68

A hardware component library developed with ROHD.

Open Nic Shell ⭐ 67

AMD OpenNIC Shell includes the HDL source files

Fpga Tamagotchi ⭐ 66

Tamagotchi P1 for Analogue Pocket and MiSTer

Register_interface ⭐ 66

Generic Register Interface (contains various adapters)

Kria Vitis Platforms ⭐ 66

Kria KV260 Vitis platforms and overlays

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。

RISC-V Zve32x Vector Coprocessor

FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Fpga Png Decoder ⭐ 57

An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图象解码器，可以从PNG文件中解码出原始像素。

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