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Search results for systemverilog uvm
systemverilog
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uvm
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28 search results found
Core V Verif
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359
Functional verification project for the CORE-V family of RISC-V cores.
Surelog
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325
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Tvip Axi
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276
AMBA AXI VIP
Rggen
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261
Code generation tool for configuration and status registers
Hwt
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189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Open Register Design Tool
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169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Logic
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121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Tnoc
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92
Network on Chip Implementation written in SytemVerilog
Peakrdl
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48
Control and status register code generator toolchain
Async_fifo
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41
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
Uvm_gen
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35
UVM Generator
Ahb To Apb Bridge Verification
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34
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
Yamm
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18
YAMM package repository
Rggen
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17
This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
Rggen Sample Testbench
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14
Dvcon_download
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14
Download proccedings from DVCon
Custom_uvm_report_server
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14
Customized UVM Report Server
Int_fp_mac
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12
INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
Uvm_tb_cross_bar
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11
SystemVerilog UVM testbench example
Rggen Systemverilog
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9
SystemVerilog RTL and UVM RAL model generators for RgGen
Isp_uvm
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9
A Framework for Design and Verification of Image Processing Applications using UVM
Uvm_candy_lover
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8
🍬UVM candy lover testbench which uses YASA as simulation script
Uvm Basics
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8
my UVM training projects
Uvm
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7
Standard Universal Verification Methodology
Yasauvk
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7
🐛UVM verification kits which uses YASA as simulation script
Axi_to_spi
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7
Designing means to communicate as an SPI master, being a part of AXI interface
Uvm_debug
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6
UVM interactive debug library
Go.debug
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5
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
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