Awesome Open Source

Programming Languages

Search results for python systemverilog

systemverilog x

29 search results found

Edalize ⭐ 573

An abstraction library for interfacing EDA tools

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Hdlconvertor ⭐ 258

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Hdl_checker ⭐ 136

Repurposing existing HDL tools to help writing better code

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Ipxact2systemverilog ⭐ 55

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Control and Status Register map generator for HDL projects

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

Control and status register code generator toolchain

Peakrdl Regblock ⭐ 36

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

CoreIR Symbolic Analyzer

SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)

Deepsocflow ⭐ 28

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Crash_course_for_new_members ⭐ 26

Deep Learning & VLSI Crash Course for New Members

Hdlconvertorast ⭐ 25

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

LLVM based HLS library for HWToolkit (hardware devel. toolkit)

Autd3 Old Monorepo ⭐ 15

Airborne Ultrasound Tactile Display 3

SystemVerilog FSM generator

Fpganes_release ⭐ 11

Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog

Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.

Teroshdl Documenter Demo ⭐ 9

This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

Blockwork ⭐ 9

An opinionated build environment for EDA projects

Open source RTL simulation acceleration on commodity hardware

Python library for parsing module definitions and instantiations from SystemVerilog files

Pysvmodel ⭐ 7

An abstract language model of SystemVerilog (incl. Verilog) written in Python.

SystemVerilog & Verilog Module I/O parser and printer

Provides a packaged collection of open source EDA tools

Python Frontend For VHDL And Verilog

Sublimelinter Contrib Xsim ⭐ 5

Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

Pythondata Cpu Blackparrot ⭐ 5

Python module containing system_verilog files for blackparrot cpu (for use with LiteX).

Sphinx Verilog Domain ⭐ 5

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

Related Searches

Python Django (28,897)

Python Machine Learning (20,195)

Python Flask (17,643)

Python Dataset (14,792)

Python Docker (14,113)

Python Tensorflow (13,736)

Python Command Line (13,351)

Python Deep Learning (13,092)

Python Jupyter Notebook (12,976)

Python Network (11,495)

1-29 of 29 search results

Privacy | About | Terms | Follow Us On Twitter

Copyright 2018-2024 Awesome Open Source. All rights reserved.